KR960015930B1 - Method for manufacturing bipolar transistor - Google Patents

Method for manufacturing bipolar transistor Download PDF

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KR960015930B1
KR960015930B1 KR1019880012211A KR880012211A KR960015930B1 KR 960015930 B1 KR960015930 B1 KR 960015930B1 KR 1019880012211 A KR1019880012211 A KR 1019880012211A KR 880012211 A KR880012211 A KR 880012211A KR 960015930 B1 KR960015930 B1 KR 960015930B1
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bipolar transistor
emitter region
photoresist
region
base
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KR900005614A (en
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황이연
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엘지전자 주식회사
최근선
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

forming an oxide film(22) after forming an epitaxial layer(21) on a semiconductor substrate; leaving the oxide film(22) on a region where an emitter region is formed; forming a base region(24,24') after a photolithography using a photoresist(23); and removing the oxide film(22) on the emitter region form the emitter region(25) by the photolithography using the photoresist(23'), a thermal process and an ion-implantation.

Description

바이폴러 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

제1도는 종래의 트랜지스터 구조도.1 is a conventional transistor structure diagram.

제2도는 본 발명의 제조공정도.2 is a manufacturing process diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11, 21 : n-에피택셜층 12, 25 : 에미터영역11, 21: n - epitaxial layer 12, 25: emitter region

13, 24, 24' : 베이스영역, 14p+영역 22 : 산화막층(SiO2층)13, 24, 24 ': base region, 14p + region 22: oxide layer (SiO 2 layer)

23, 23' : 포토레지스터23, 23 ': photoresistor

본 발명은 샐로우(shal1ow) 정크션 구조를 갖는 반도체 소자의 바이폴러 트랜지스터에 관한 것으로, 특히 베이스의 패시브(Passive) 저항값을 줄여 주파수 및 전기적 특성이 향상되게 한 바이폴러 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor of a semiconductor device having a shallow junction structure, and more particularly, to a method of manufacturing a bipolar transistor in which a frequency and electrical characteristics are improved by reducing a passive resistance value of a base. .

일반적으로 샐로우 정크션 구조의 반도체 소자에서 이득률(hFE)

Figure kpo00002
을 정크션 구조에 관계없이 일정하게 하기 위해 베이스 전류(IB)를 제어하려면, 베이스 저항값이 높아야 하므로 베이스의 도핑농도를 낮게 해야 한다.In general, the gain ratio (h FE ) in a shallow junction structure semiconductor device.
Figure kpo00002
In order to control the base current I B to make the constant constant regardless of the junction structure, the base doping concentration must be low because the base resistance value must be high.

그러나 이 경우 베이스의 패시브 저항값이 커져 노이즈가 커지는 문제점이 있었다.In this case, however, the passive resistance value of the base is increased, resulting in a large noise.

이런 문제점을 해결코자 종래에는 제1도의 (a)와 같이 베이스영역(13)과 에미터영역(l2)을 가진 트랜지스터에 제1도의 (b)와 같이 p+영역(14)을 만들어 베이스의 패시브 저항값을 줄였으나, p+영역(l4)을 만드는 공정으로 인해 전체 공정이 복잡하고, 이 공정에 p+마스크(Mask)가 소요되므로 비용상승의 원인이 되었다.To solve this problem, conventionally, p + regions 14 are formed in a transistor having a base region 13 and an emitter region l2 as shown in FIG. Although the resistance value was reduced, the overall process was complicated by the process of creating the p + region (l4), which caused a cost increase because the process requires a p + mask.

본 발명은 이와같은 종래의 결점을 없애기 위해 공정을 간단히 하고. 그에 따라 비용이 절감되게 창안한 것으로서, 이를 본 발명의 제조공정도인 제2도에 의하여 상세히 설명하면 다음과 같다.The present invention simplifies the process to eliminate this conventional drawback. Accordingly, the present invention is designed to reduce the cost, which will be described in detail with reference to FIG. 2, which is a manufacturing process diagram of the present invention.

제2도의 (a)와 같이 n-에피택셜층(21)을 형성한 후 산화막(22)을 형성하고, 세2도의 (b)와 같이 에미터영역이 될 부분의 산화막(22)만 남도록 에칭하며, 제2도의 (c)와 같이 포토레지스터(23)를 도포한 후, 베이스영역이 될 부분을 사진식각함과 아울러, 제2도의 (d)와 같이 저농도의 이온주입에 의해 베이스영역(24, 2')을 형성한 후, 제2도의 (e)와 같이 산화막(22)을 제거하고, 포트레지스터(23')를 도포한 후 에미터영역이 될 부분을 사진식각하며, 제2도의 (f)와 같이 열처리 후 이온주입에 의해 에미터영역(25)을 형성함으로써 본 발명의 바이폴러 트랜지스터를 제조한다.After forming the n − epitaxial layer 21 as shown in FIG. 2 (a), the oxide film 22 is formed, and as shown in FIG. After the photoresist 23 is coated as shown in FIG. 2 '), the oxide film 22 is removed as shown in (e) of FIG. 2, the photoresist 23' is applied, and a portion of the emitter region is photographed. The bipolar transistor of the present invention is manufactured by forming the emitter region 25 by ion implantation after heat treatment as in f).

이와같이 제조되는 바이폴러 트랜지스터에 있어서, 베이스영역(24)의 도핑농도를 베이스영역(24')의 도핑농도보다 임의로 낮게 하여 베이스영역(24)의 패시브 저항값을 낮출 수 있어 노이즈를 줄여 나갈 수 있다.In the bipolar transistor manufactured as described above, the dopant concentration of the base region 24 is arbitrarily lower than the dopant concentration of the base region 24 'so that the passive resistance value of the base region 24 can be lowered, thereby reducing noise. .

이상의 상세한 설명과 같이 본 발명은 샐로우 정크션 구조의 바이폴러 트랜지스터를 제조할 때 베이스 저항값을 임의대로 설정할 수 있고, 이때 발생하는 베이스의 패시브 저항값을 감소시킬 수 있어 노이즈가 적은 트랜지스터를 제조할 수 있을 뿐 아니라, 공정이 간단해지므로 비용을 절감할 수 있는 효과가 있다.As described above, the present invention can arbitrarily set a base resistance value when manufacturing a bipolar transistor having a shallow junction structure, and reduce a passive resistance value of a base generated at this time, thereby manufacturing a transistor having low noise. Not only can this be done, but the process can be simplified, resulting in cost savings.

Claims (1)

반도체 기판위에 에피택셜층(21)을 형성한 후 산화막(22)을 형성하고, 에미터영역이 형성될 부분에만 상기 산화막(22)이 남게 하고, 포토레지스터(23)를 이용하여 사진식각한 후 베이스영역(24, 24')을 형성하고, 상기한 에미터영역의 산화막(22)을 제거함과 아울러 포토레지스터(23')를 이용해 사진식각, 열처리 및 이온주입으로 에미터영역(25)을 형성하는 것을 특징으로 한 바이폴러 트랜지스터 제조방법.After the epitaxial layer 21 is formed on the semiconductor substrate, the oxide layer 22 is formed, the oxide layer 22 remains only at the portion where the emitter region is to be formed, and the photoresist is photo-etched using the photoresist 23. The base regions 24 and 24 'are formed, the oxide layer 22 of the emitter region is removed, and the emitter region 25 is formed by photolithography, heat treatment, and ion implantation using the photoresist 23'. Bipolar transistor manufacturing method characterized in that.
KR1019880012211A 1988-09-21 1988-09-21 Method for manufacturing bipolar transistor KR960015930B1 (en)

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KR960015930B1 true KR960015930B1 (en) 1996-11-23

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