KR960015888A - Semiconductor power device and manufacturing method thereof - Google Patents

Semiconductor power device and manufacturing method thereof Download PDF

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KR960015888A
KR960015888A KR1019940026969A KR19940026969A KR960015888A KR 960015888 A KR960015888 A KR 960015888A KR 1019940026969 A KR1019940026969 A KR 1019940026969A KR 19940026969 A KR19940026969 A KR 19940026969A KR 960015888 A KR960015888 A KR 960015888A
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diffusion region
region
power device
semiconductor power
collector
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KR1019940026969A
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KR0134847B1 (en
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박훈수
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 전력소자 및 그 제조방법이 개시된다.The present invention discloses a semiconductor power device and a method of manufacturing the same.

본 발명은 Bi-M0S형(바이폴라 트랜지스터와 M0S 트랜지스터 결합형)전력소자에서, M0S 트랜지스터를 LDMOS(LateralDiffusedMOS)로구현한다. MOS트랜지스터는 바이폴라(Bipolar)트랜지스터의 에미터(Emhter)를 중심으로 대칭되게 구현한다. 바이폴라 트랜지스터의 콜렉터(Collector) 는 메몰층(Buried Layer)과 연결되도록 깊게 형성한다. 그리고, LDMOS와 바이폴라 트랜지스터의 모든 전극은 칩(Chip)상부에 배치되도록 한다.The present invention implements the M0S transistor as LDMOS (Lateral DiffusedMOS) in a Bi-M0S type (bipolar transistor and M0S transistor combined type) power device. The MOS transistor is implemented symmetrically around the emitter of a bipolar transistor. The collector of the bipolar transistor is formed to be deeply connected to the buried layer. All electrodes of the LDMOS and the bipolar transistors are arranged on the chip.

따라서, 본 발명은 전류구동능력이 우수한 단 채널(shod channel)CM0S 회로와 동일 칩상에 구현시킬 수 있어 제어회로와 구동회로가 포함된 스마트 전력 집적회로(Smart Power IC) 구현에 적합하다.Therefore, the present invention can be implemented on the same chip as the short channel CM0S circuit having excellent current driving capability, and thus is suitable for implementing a smart power integrated circuit (Smart Power IC) including a control circuit and a driving circuit.

Description

반도체 전력소자 및 그 제조방법Semiconductor power device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 의한 반도체 전력소자의 단면도,1 is a cross-sectional view of a semiconductor power device according to the present invention,

제2도는 제1도의 등가회로도.2 is an equivalent circuit diagram of FIG.

Claims (13)

Bi-M0S형 반도체 전력소자에 있어서, 반도체 기판위에 선택적으로 형성된 매몰층과, 상기 메몰층을 포함한 웨이퍼 전면에 에피텍셜 성장법으로 성장된 에피충과, 상기 에피층의 소정부분에 일정폭과 접합깊이를 갖는 터브와, 상기 터브의 소정부분에 형성된 에미터 확산영역과, 상기 에미터 확산영역을 중심으로 상기 터브의 소정부분에 대칭되게 형성된 소스 및 베이스 접합영역과, 상기 에미터 확산영역을 중심으로 상기 소스 및 베이스 확산영역 의측에 대칭되게 형성된 게이트 전극과, 상기 에미터 확산영역을 중심으로 상기 게이트 전극의측에 대칭되게 형성된 콜렉더/드레인 확산영역과. 상기 콜렉터/드레인 확산영역으로부터 연장되어 상기 메몰층과 연결된 딥 콜렉터 및, 상기 딥 콜렉터의 외측에서 상기 애피층을 통해 하부의 반도체 기판과 연결된 격리영역으로 구성된 것을 특징으로 하는 LDMOS 트랜지스터와 바이폴라 트랜지스터가 결합된 구조의 반도체 전력소자.A Bi-M0S type semiconductor power device, comprising: a buried layer selectively formed on a semiconductor substrate, epitaxially grown on the entire surface of the wafer including the buried layer by epitaxial growth, and a predetermined width and a junction depth at a predetermined portion of the epilayer. A tub having a center, an emitter diffusion region formed at a predetermined portion of the tub, a source and base junction region symmetrically formed at a predetermined portion of the tub with respect to the emitter diffusion region, and the emitter diffusion region A gate electrode symmetrically formed on the sides of the source and base diffusion regions, and a collector / drain diffusion region symmetrically formed on the side of the gate electrode around the emitter diffusion region; An LDMOS transistor and a bipolar transistor coupled to a deep collector connected to the buried layer extending from the collector / drain diffusion region, and an isolation region connected to a lower semiconductor substrate through the epitaxial layer outside the deep collector. Semiconductor power devices. 제1항에 있어서, 상기 반도체 기판, 터브, 베이스 접합영역 및 격리영역을 P형으로 형성하고, 상기 매몰층, 에피층, 딥 콜렉터, 소스 확산영역, 에미터 확산영역 및 콜렉터/드레인 확산영역을 N형으로 형성하여 NMOS(LDMOS)트랜지스터와 NPN 바이폴라 트랜지스터가 결합된 구조로 이루어진 것을 특징으로 하는 반도체 전력소자.The semiconductor device of claim 1, wherein the semiconductor substrate, the tub, the base junction region, and the isolation region are formed in a P type, and the buried layer, the epi layer, the deep collector, the source diffusion region, the emitter diffusion region, and the collector / drain diffusion region are formed. A semiconductor power device comprising an N-type transistor and an NMOS transistor and an NPN bipolar transistor. 제1항에 있어서, 상기 반도체 기판, 터브, 베이스 접합영역 및 격리영역을 N형으로 형성하고, 상기 메몰층, 에피층, 딥 콜렉터, 소스 확산영역, 에미터 확산영역 및 콜렉터/드레인 확산영역을 P형으로 형성하여 PMOS(LDMOS)트탠지스터와 PNP 바이폴라 트랜지스터가 결합된 구조로 이루어진 것을 특징으로 하는 반도체 전력소자.The semiconductor device of claim 1, wherein the semiconductor substrate, the tub, the base junction region, and the isolation region are formed in an N type, and the buried layer, epi layer, deep collector, source diffusion region, emitter diffusion region, and collector / drain diffusion region are formed. A semiconductor power device formed of a P-type and having a structure in which a PMOS (LDMOS) transistor and a PNP bipolar transistor are combined. 제1항에 있어서, 상기 터브는 LDMOS 드랜지스터의 채널영역인 것을 특징으로 하는 반도체 전력소자.The semiconductor power device of claim 1, wherein the tub is a channel region of an LDMOS transistor. 제1항에 있어서, 상기 에미터 확산영역과 상기 베이스 접합영역은 필드 산화막으로 분리되어 표면에서의 항복현상을 방지하는 것을 특징으로 하는 반도체 전력소자.The semiconductor power device as claimed in claim 1, wherein the emitter diffusion region and the base junction region are separated by a field oxide layer to prevent breakdown at the surface. 제1항에 있어서, 상기 베이스 접합영역은 바이폴라 트랜지스터의 베이스 전극 역할과 LDMOS의 터브를 접지시키는 역할을 동시에 수행하는 것을 특징으로 하는 반도체 전력소자.The semiconductor power device of claim 1, wherein the base junction region simultaneously serves as a base electrode of a bipolar transistor and grounds a tub of an LDMOS. 제1항에 있어서, 상기 메몰층과 상기 딥 콜렉터가 연결되어 콜렉터 저항을 줄이는 것을 특징으로 하는 반도체 전력소자.The semiconductor power device of claim 1, wherein the buried layer and the deep collector are connected to reduce a collector resistance. 제1항에 있어서, 상기 소스 확산영역과 상기 배이스 접합영역은 간격없이 상호 접속되게 형성된 것을 특징으로 하는 반도체 전력소자.The semiconductor power device of claim 1, wherein the source diffusion region and the base junction region are formed to be interconnected without a gap. 제1 또는 제8항에 있어서, 상기 소스 확산영역과 상기 베이스 접합영역은 각각 다른 불순물 타입으로 형성된 것을 특징으로 하는 반도체 전력소자.9. The semiconductor power device of claim 1 or 8, wherein the source diffusion region and the base junction region are each formed of a different impurity type. 제1항에 있어서, 상기 터브의 불순물 도핑종도와 접합깊이를 조잘하여 출력전류를 조절하는 것을 특징으로 하는 반도체 전력소자.The semiconductor power device as claimed in claim 1, wherein the output current is controlled by adjusting the doping dopant depth and junction depth of the tub. Bi-MOS형 반도체 전력소자의 제조방법에 있어서, P형 반도체 기판위에 선택적으로 N & 매몰층을 형성하고, 웨이퍼 전면에 N형 에피층을 성장한 후 소자 격리를 목적으로 P & 격리영역을 형성하는 단계와, 상기 단계로부터 N & 매몰층과 연결되는 N & 딥 콜렉터를 형성한 후 N형 에피층 소정부분에 P형 터브를 형성하는 단계와, 상기 단계로부터 소자간 또는 접합간을 격리시키기 의하여 필드 산화막을 소정 간격으로 다수개 형성한 후 P형 터브와 필드 산화막상의 특정부위에 위치되며 대칭되게 게이트 산화막 및 게이트 전극을 형성하는 단계와, 상기 단계로부더 LDMOS 트랜지스터의 소스 및 드레인과 NPN 바이폴라 트랜지스터의 에미터 확산영역을 형성하기 위해 N·불순물 주입공정으로 다수의 N & 확산영역을 형성한 후 P·불순을 주입공정으로 베이스 확산영역을 형성하는 단계와, 상기 단계로부터 절연막 형성 및 금속콘택 공정으로 LDMOS 트랜지스터의 소스 및 드레인 전극과 NPN 바이폴라 트랜지스터의 에미터 및 콜렉터 전극을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 전력소자의 제조방법.In the method of manufacturing a Bi-MOS semiconductor power device, an N & buried layer is selectively formed on a P-type semiconductor substrate, an N-type epitaxial layer is grown on the entire surface of the wafer, and a P & I isolation region is formed for device isolation. Forming an N & deep collector connected to the N & buried layer from the step, and then forming a P type tub in a predetermined portion of the N type epi layer, and isolating the field or junction between the elements from the step. Forming a plurality of oxide films at predetermined intervals, and then forming gate oxide films and gate electrodes symmetrically positioned at specific portions on the P-type tub and the field oxide film, wherein the source and drain of the LDMOS transistor and the NPN bipolar transistor After forming a large number of N & D diffusion regions by the N · impurity implantation process to form the emitter diffusion region, the base diffusion region by the P · impurity implantation process Forming, and a method for manufacturing a semiconductor power device, characterized in that comprising the step of forming from the step emitter and collector electrodes of the source and drain electrodes and an NPN bipolar transistor of the LDMOS transistor with an insulating film forming step and the metal contact. 제11항에 있어서, 상기 N & 소스 확산영역과 P & 베이스 접합영역은 상호 접속되게 형성시키며, 상기 N & 에미터 확산영역은 상기 P & 베이스 접합영역과 필드 산화막에 의해 분리되도록 형성시키는 것을 특징으로 하는 반도체 전력소자의 제조방법.The method of claim 11, wherein the N & source diffusion region and the P & base junction region are formed to be interconnected, and the N & emitter diffusion region is formed to be separated by the P & base junction region and the field oxide film. A method of manufacturing a semiconductor power device. 제11항에 있어서, 상기 LDMOS 트랜지스터의 N & 드레인 확산영역은 상기 N & 딥 콜렉터 상부에 형성되는 것을 특징으로 하는 반도체 전력소자의 제조방법.The method of claim 11, wherein the N & drain diffusion region of the LDMOS transistor is formed above the N & deep collector. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940026969A 1994-10-21 1994-10-21 Semiconductor power device and manufacturing method thereof KR0134847B1 (en)

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