KR960015365B1 - Test unit for speech path - Google Patents

Abstract

a reset circuit(109A) which provides a pulse making a test data stored in a shift register(113) by receiving the channel selection signal from a channel selection part(108) be loaded in an input data latch part(111), and stops the loading after some period and disables an apparatus selecting and channel selecting signal by sending the reset signal to a channel selecting part(107); and an apparatus selecting part(114) outputting the channel selecting signal provided from a subscriber accepting apparatus interface part and the channel selecting part(107).

Description

Test device for time division switch call considering subscriber capacity

1 is a block diagram of a conventional test path test apparatus.

2 is a connection diagram in which a device incorporating a test apparatus according to the prior art is applied to a subscriber interface device of an electronic switching system.

3 is a block diagram according to an embodiment of the present invention.

4 is a connection diagram in which a device incorporating a test apparatus according to the present invention is applied to a subscriber interface device of an electronic switching system.

5 is an internal configuration diagram of the subscriber receiver matching device of FIG.

6 is a timing diagram of a test data write operation according to the present invention.

7 is a timing diagram of a test data read operation in accordance with the present invention.

* Explanation of symbols for main parts of the drawings

100: processor 101: processor interface unit

102: write latch 103: read latch

104 and 105: Comparator 106: Latch and Register

107 and 108: channel selection section 111: input data latch section

112: test data output section 113: shift register

109: counter 114: device selection unit

The present invention relates to a test apparatus for an all-electronic switch call path, and more particularly, to a time-division switch call test capable of maximally accommodating subscriber telephone channel capacity in a local subsystem while smoothly performing a test with a call of a time-division switch of an all-electronic switch. Relates to a device.

Looking at the prior art with reference to Figures 1 and 2 as follows.

1 is a configuration diagram of a test apparatus of a conventional currency, in which 100 is a processor, 101 is a processor interface unit, 102 is a write latch, 103 is a read latch, 104 and 105 are comparators, 106 is a latch and a register; Reference numerals 107 and 108 denote channel selectors, 111 denote input data latches, 112 denote test data outputs, and 113 denote shift registers.

When a test control signal is transmitted from the processor 100 by a call, when the test data is written, the test control signal is received by the processor interface unit 101 and latched by the write latch 102. The comparator 104 compares a control signal latched to the write latch 102 with a corresponding bit divided by the reference clock provided by the counter 109 to select a channel requested by the processor 100 and to output a test data output unit. Output for use as the enable signal of 112.

The latch and register 106 converts the test control signal input from the processor interface unit 101 into a latch and serial data to an externally provided reference clock and sends the test control signal to the test data output unit 112. Via 112 is sent to the subscriber receiving device matching device (TSIA).

Referring to the operation according to the test data reading, the test control signal from the processor interface unit 101 is latched in the read latch 103, and the latched signal is compared with the corresponding bit which is the output of the counter 109 in the comparator 105. Select the channel.

On the other hand, when serial data is input from the subscriber acceptor matching device to the decoder 110, the decoder 110 is selected by the test control signal stored in the read latch 103, and the serial data from the subscriber acceptor matching device. The input data is temporarily stored in the shift register 113 by the reference clock and is input by the input data latch unit 111 by the output signal of the channel selector 108 that selects a channel according to the signal provided by the comparator 105. ) Is periodically loaded, and is compared with the test data which is read by the processor 100 control and written when writing the test data.

2 is a connection diagram in which a device incorporating a test device according to the prior art is applied to a subscriber interface device of an electronic switch, wherein 201 to 204 are subscriber receiver matching devices, and 205 is a test circuit incorporating a test device according to the present invention. Device (CMMA).

As shown in the figure, the subscriber acceptor matching units 201 to 204 have 32 input / output subhighways, and one subhighway can accommodate 32 subscriber channels. Sub highways 0 to 30 are connected to the subscriber terminal, and sub highway 31 is connected to the test circuit built-in device 205 and the subscriber terminal. Accordingly, the test data output unit 112 of FIG. 1 occupies the corresponding subhighway by enabling and disabling when testing a telephone line, so that the 31st sub of the subscriber accommodating unit matching unit 201 to 204 is used for the test. The highway will not actually be able to accommodate subscribers.

The problems of the prior art discussed above are as follows.

1) In the off-line state, it can be used as a device check function in the time division switch, but in the on-line state, the subhighway must be used for the test function or the subscriber matching function. have.

2) When using sub-highway 31 as an on-line test function, it is not possible to accommodate 32 subscribers per subscriber acceptor matching device at the maximum accommodating subscriber capacity in the local subsystem (eg 4096 subscribers). .

In addition, the shape of the cable connected between the time division switch and the subscriber receiving device must also be changed.

3) After completion of the test function in the on-line state, the test signal output interrupt 112 is transmitted from the write latch 102 to the channel selector 107 by the processor control. You have to.

Accordingly, the present invention has been made to solve the problems of the prior art as described above, the channel selection signal and the test data in units of subscriber receiving device matching device that matches with the subscriber receiving device in the time-division switch internal test circuit device Time-slicing switch that can transmit and accommodate the maximum subscribers per local subsystem, and the channel selection signal is automatically removed without the processor's control when the test is over by the call so that the channel used for the test can receive normal telephone service. Its purpose is to provide a test apparatus with currency.

In order to achieve the above object, the present invention, in the test data currency test apparatus shown in Fig. 1, receives the channel selection signal from the channel selection unit 108 and inputs the test data temporarily stored in the shift register 113. It provides a pulse to be periodically loaded to the data latch 111, stops the load after a certain period and sends a reset signal to the channel selector 107 to deactivate the device selection and channel selection signal And a device selection means for receiving a device selection control signal from the writing latch 102 and outputting a channel selection signal provided from the channel selection unit 107 to the selected subscriber receiving device matching unit.

In addition, the channel selection signal is output from the comparator 104 to the latch and the register 106 so that the test data is output only in the selected channel.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a configuration diagram according to an embodiment of the present invention, in which 109A denotes a reset circuit, 114 denotes a device selector, and the same reference numerals as in FIG. 1 denote the same components.

When the channel selection control signal is transmitted from the processor 100 through a call, the processor interface unit 101 receives the channel selection control signal when the test data is written, and latches it in the write latch 102. The comparator 104 receives and compares the control signal latched to the write latch 102 with the corresponding bit divided by the reference clock provided by the counter 109 to compare the channel requested by the processor 100 with the channel selector 107. ) To be input to the device selector 114 connected to the output of the channel selector 107.

Accordingly, the device selection unit 114 receives the device selection control signal from the write latch 102 and sends a channel selection signal to the selected subscriber receiving device matching unit.

The latch and the register 106 latch the test control signal input from the processor interface unit 101 to a reference clock provided externally, convert the test control signal into serial data, receive the channel selection signal from the comparator 104, and then test data only on the selected channel. Is transmitted to the subscriber receiving device matching unit through the test data output unit 112.

Referring to the operation according to the test data reading, the control signal from the processor interface unit 101 is latched to the read latch 103, and the latched signal is compared with the corresponding bit which is the output of the counter 109 in the comparator 105. Select the channel.

On the other hand, when the serial data is input to the decoder 110 from the subscriber acceptor matching unit, the decoder 110 selects the decoder 110 by the control signal stored in the read latch 103, which is the serial data from the subscriber acceptor matching unit. The input data is temporarily stored in the shift register 113 by the reference clock.

The reset circuit 109A connected to the channel selectors 107 and 108 and connected to the output terminal of the processor interface unit 101 receives the channel select signal from the channel selector 108 and inputs test data temporarily stored in the shift register 113. It is periodically loaded to the data latch unit 111, and after two cycles, the load is stopped and a reset signal is sent to the channel selector 107 to deactivate the device selector and the channel select signal of the device selector 114. The test data loaded in the input data latch unit 111 is read by the processor 100 control and compared with the test data written when writing the test data to determine whether there is an abnormality in the call path.

4 is a connection diagram in which a device having a test device according to the present invention is applied to a subscriber interface device of an electronic switch, in which 401 to 404 are subscriber receiving device matching devices, and 405 is a test device according to the present invention. Represents a device.

The subscriber receiving device matching device 401 to 40 has 32 input / output subhighways, and one subhighway can accommodate 32 subscriber channels. Sub-highways 0 to 31 are connected to the subscriber end, and since the test data and the channel selection signal are received from the test circuit built-in device 405, all the sub-highways can accommodate the subscriber.

FIG. 5 is an internal configuration diagram of the device of the subscriber receiver matching units 401 to 404 of FIG. 4, where 501 denotes a data selector and 502 a multiplexer.

The data selector 501 selects and outputs the subhighway data 31 and the test data from the subscriber end by the channel select signal, and the multiplexer 502 receives the output signal of the data selector 501 to receive the subscriber. The signal is multiplexed with the 0 to 30 subhighway signals from the stages and output. By doing so, the 31st subhighway was used online for testing and subscriber acceptance in a time-division switch call.

6 is a timing diagram of a test data write operation according to the present invention.

In the drawing, SCLK, FS, MA0 to MA3, and TXD represent a control signal output from the processor 100 to the processor interface unit 101, and RDY indicates a ready signal sent from the selected device to the processor 100 according to the control signal. Indicates. A is a rising edge of the latch clock provided to the latch and the register 106, and latches the test data at this point.

7 is a timing diagram of a test data read operation according to the present invention.

In the figure, b and c represent the rising edges of the latch clocks provided by the reset circuit 109A to the input data latch unit 111, and the test data temporarily stored in the shift register 113 at b and c is It is loaded in the input data latch section 111. The signal d transmitted from the reset circuit 109A to the channel selector 107 is generated by the / Q and Q (t + 1) signals generated by the reset circuit 109A. All output signals of 107 are made high.

Therefore, the present invention configured and operated as described above can accommodate the maximum subscribers per local subsystem when on-line, and when the test is completed by the call, the channel selection signal is automatically disappeared without the control of the processor and used for the test. The channel that was used also has the effect of receiving normal telephone service.

Claims (2)

A processor 100 for providing a channel selection control signal through a call, a processor interface unit 101 for receiving the channel selection signal from the processor 100, and latching the channel selection control signal in a test data write mode; A comparator 104 for receiving a write latch 102, a control signal latched to the write latch 102, and a corresponding bit divided by a reference clock provided by the counter 109, and outputting a result; A channel selector 107 for receiving the output of the comparator 104 and the device selection control signal provided by the write latch 102 and selecting a channel requested by the processor 100, and the processor interface unit ( 101 is a reference clock externally provided with the test control signal inputted from the controller, latched and converted into serial data to receive a channel selection signal from the comparator 104, and then the test data is received only from the selected channel. Latch and register 106 for outputting to the subscriber receiving device matching unit through the test data output unit 112 so that the data is transmitted, and for reading to latch the control signal from the processor interface unit 101 in the test data read mode. A latch 103, a comparator 105 for receiving and comparing the output of the reading latch 103 and a corresponding bit that is an output of the counter 109, and receiving and outputting the output of the comparator 105; A channel selector 108 for selecting a channel to read the decoder, a decoder 110 for selecting serial data from an external subscriber receiver matching unit using a control signal stored in the read latch 103, and the decoder A shift register 113 for temporarily storing serial data from the subscriber accommodation device matching section selected by 110 by a reference clock, and an input for loading the output of the shift register 113. In the test data communication path of an electronic switch provided with a latch latch 111, the test data received from the channel selector 108 receives the channel select signal and is temporarily stored in the shift register 113. And a reset circuit 109A for stopping the load after a predetermined period and sending a reset signal to the channel selector 107 to deactivate the device selection and channel selection signals. ; And a device selector 114 which receives a device selection control signal from the write latch 102 and outputs a selected subscriber receiver matching device and a channel selector signal provided by the channel selector 107. Apparatus for testing time-divided switches in consideration of subscriber capacity. The apparatus of claim 1, wherein the channel select signal is output from the comparator to the latch and the register so that the test data is output only in the selected channel.