KR960015252A - Common RAM access control method and device - Google Patents
Common RAM access control method and device Download PDFInfo
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- KR960015252A KR960015252A KR1019940027968A KR19940027968A KR960015252A KR 960015252 A KR960015252 A KR 960015252A KR 1019940027968 A KR1019940027968 A KR 1019940027968A KR 19940027968 A KR19940027968 A KR 19940027968A KR 960015252 A KR960015252 A KR 960015252A
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- common ram
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Abstract
본 발명은 공용램 억세스 제어방법 및 장치에 관한 것으로서, 이는 공용램을 담당하는 전용 프로그램 모듈과 타스크 버퍼를 사용하여 공용램에 보내고자 하는 데이타의 저장장소를 알려주어 공용램의 억세스 시간손실과 비효율성을 제거하도록 한 것이다.The present invention relates to a method and apparatus for controlling access to a common RAM, which uses a dedicated program module and a task buffer for a common RAM to inform a storage location of data to be sent to the common RAM to prevent access time loss and non-access of the common RAM. It is to remove efficiency.
이와 같은 본 발명은 공용램에 보내고자 하는 데이타가 저장되어 있는 영역에 대한 정보를 적어도 하나 이상의 프로그램 모듈로부터 순차 입력 받아 저장하는 단계와, 상기 저장된 각 프로그램 모듈의 정보들을 파악하여 첫번째 수순의 프로그램 모듈서부터 마지막 순서의 프로그램 모듈의 정보중에 어느 하나의 프로그램 모듈의 정보가 존재하면 그 정보에 해당하는 영역의 데이타를 공용램에 전달하여 주는 단계와, 상기 프로그램 모듈의 정보들을 파악한 결과 첫번째 프로그램 모듈서부터 마지막 프로그램 모듈의 정보가 존재하지 않으면 공용램의 억세스를 해제하는 단계로 이루어짐으로서, 달성된다.As described above, the present invention comprises sequentially receiving and storing information on an area in which data to be sent to a common RAM is stored from at least one program module, and grasping the information of each stored program module to obtain a first program module. If the information of any one of the program module information from the last sequence from the first to the last step of the step of delivering the data of the area corresponding to the information to the common RAM, and the information of the program module as a result of the first program module from the last If the information of the program module does not exist, it is achieved by the step of releasing access to the common RAM, it is achieved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제3도는 본 발명 공용램 억세스 제어장치의 블록 구성도,3 is a block diagram of a common RAM access control apparatus of the present invention;
제4도는 프로그램 모듈의 수순에 따른 억세스 상태를 보인 신호흐름도,4 is a signal flow diagram showing an access state according to a procedure of a program module,
제5도는 제4도에서의 전용 프로그램 모듈에 의해 공용램을 억세스하는 신호흐름도.5 is a signal flow diagram of accessing the common RAM by the dedicated program module in FIG.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940027968A KR960015252A (en) | 1994-10-28 | 1994-10-28 | Common RAM access control method and device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940027968A KR960015252A (en) | 1994-10-28 | 1994-10-28 | Common RAM access control method and device |
Publications (1)
Publication Number | Publication Date |
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KR960015252A true KR960015252A (en) | 1996-05-22 |
Family
ID=66687302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019940027968A KR960015252A (en) | 1994-10-28 | 1994-10-28 | Common RAM access control method and device |
Country Status (1)
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KR (1) | KR960015252A (en) |
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1994
- 1994-10-28 KR KR1019940027968A patent/KR960015252A/en not_active Application Discontinuation
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