KR960014955B1 - Oxide layer deposition method - Google Patents
Oxide layer deposition method Download PDFInfo
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- KR960014955B1 KR960014955B1 KR1019930016028A KR930016028A KR960014955B1 KR 960014955 B1 KR960014955 B1 KR 960014955B1 KR 1019930016028 A KR1019930016028 A KR 1019930016028A KR 930016028 A KR930016028 A KR 930016028A KR 960014955 B1 KR960014955 B1 KR 960014955B1
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- oxide film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
Abstract
Description
제1도는 종래의 기술에 의한 산화막 형성 단면도.1 is a cross-sectional view of oxide film formation according to the prior art.
제2도는 본 발명에 사용된 PE-CVD 구성도.2 is a PE-CVD configuration used in the present invention.
제3도는 본 발명의 산화막 형성 메카니즘을 설명하기 위한 단면도.3 is a cross-sectional view for explaining the oxide film formation mechanism of the present invention.
제4도는 본 발명에 의해 형성된 산화막을 나타낸 단면도.4 is a cross-sectional view showing an oxide film formed by the present invention.
제5도는 본 발명의 고주파 전압에 따른 증착율 및 굴절율 변화를 나타낸 그래프.5 is a graph showing a change in deposition rate and refractive index according to the high frequency voltage of the present invention.
제6도는 본 발명의 고주파 전력에 따른 파동수와 전송율과의 관계를 나타낸 그래프.6 is a graph showing the relationship between the wave number and the transmission rate according to the high frequency power of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반응로 2 : 고주파전극1 reactor 2 high frequency electrode
3 : 접지전극 4 : 차폐막3: grounding electrode 4: shielding film
5 : 링분배기 6 : 고주파 전원5: ring distributor 6: high frequency power supply
7 : 반도체 기판 8 : 산화막7: semiconductor substrate 8: oxide film
9 : 단차9: step
본 발명은 산화막 증착에 관한 것으로, 특히 고주파 불꽃 방전시 전극 면적변화에 따른 자기인가전압(Self-Bias) 차이를 이용하여 저온에서 스텝 커버리지(Step Coverage : 단차피복)가 우수한 실리콘 산화막을 형성하는데 적당하도록한 산화막 증착 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to oxide film deposition, and is particularly suitable for forming a silicon oxide film having excellent step coverage at a low temperature by using a self-bias difference caused by a change in electrode area during a high frequency flame discharge. It relates to an oxide film deposition method.
고주파 불꽃방전(RF glow discharge)을 이용하여 실리콘 산화막을 증착하는 종래의 기술은 반도체 기판의 온도를 200℃ 이상으로 가열한 상태에서 증착한다.The conventional technique of depositing a silicon oxide film by using a RF glow discharge (CVD) is deposited in a state in which the temperature of the semiconductor substrate is heated to 200 ° C or more.
이와 같은 종래의 기술은 제1도에 나타낸 PECVD(Plasma Enhenced CVD)를 이용한 산화막 형성 단면도와 같이 반도체 기판(7) 표면에 흡착한 종자(species)의 표면 이동도가 크기 않기 때문에, 단차(9)에 증착될 경우 그림자 효과(shadowing effect)에 의해 아래면 구석에 증착된 산화막(8) 두께가 다른 곳보다 작은 박화(Thinning) 현상이 발생하여, 증착된 산화막 내에 기포(void)가 형성되는 문제점이 있었다.This conventional technique has a large surface mobility of seeds adsorbed on the surface of the semiconductor substrate 7 as shown in the oxide film formation cross section using PECVD (Plasma Enhenced CVD) shown in FIG. When deposited on the thin film, a thinning phenomenon occurs in which the thickness of the oxide film 8 deposited in the lower corner is smaller than that of the other portions due to the shadowing effect, thereby forming a void in the deposited oxide film. there was.
본 발명은 이와 같은 종래 기술의 문제점을 해결하기 위해 안출된 것으로, 증착 반응이 일어나는 기판 표면에 이온충돌을 유도하여 단차 피복효과를 개선하고 상온에서도 증착이 가능한 산화막 증착방법 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide an oxide film deposition method that can be deposited at room temperature to improve the step coverage effect by inducing ion collision on the substrate surface where the deposition reaction occurs.
이하에서, 상기한 목적을 실현하기 위한 본 발명은 플라즈마 CVD장치가 고주파 전극의 유효면적을 줄이는 것이 특징이다.Hereinafter, the present invention for realizing the above object is characterized in that the plasma CVD apparatus reduces the effective area of the high frequency electrode.
제2도는 본 발명을 설명하기 위한 플라즈마 증착장치의 구성도를 나타낸 것으로써, 산화막 증착 공정시 기판을 실장하고 진공상태를 유지하는 반응로(1)와, 반응로(1) 하측 내부에 장착된 고주파 전극(2)과, 상측에 설치된 접지전극(3)과, 고주파 전극(2)의 측면과 상부 테두리 부분을 감싸 고주파 불꽃 방전이 접촉하는 유효 전극 면적을 제한하는 차폐막(4)과, 고주파 전극(2)과 접지전극(3) 사이에 위치하여 유입되는 가스의 밀도를 균일하게 하는 링 분배기(5)와, 고주파 전극(2)에 연결되어 고주파 전력을 발생하는 고주파 전원(6)으로 구성되며, 산화막 형성 고정시 고주파 전극(2)상에 반도체 기판(7)이 장착된다.FIG. 2 is a schematic view of a plasma deposition apparatus for explaining the present invention. The reactor 1 mounts a substrate and maintains a vacuum state in an oxide film deposition process, and is mounted inside the reactor 1 under the reactor. The high frequency electrode 2, the ground electrode 3 provided on the upper side, the shielding film 4 which limits the effective electrode area which a high frequency flame discharge contacts, surrounding the side surface and upper edge part of the high frequency electrode 2, and the high frequency electrode It is composed of a ring divider (5) located between the (2) and the ground electrode (3) to uniform the density of the gas flowing in, and a high frequency power source (6) connected to the high frequency electrode (2) to generate high frequency power. The semiconductor substrate 7 is mounted on the high frequency electrode 2 when the oxide film is fixed.
이와 같은 PECVD(Plasma Enhenced CVD) 장치를 이용한 산화막 증착의 원리를 설명하면 다음과 같다.The principle of oxide film deposition using a plasma enhanced CVD (PECVD) apparatus is as follows.
패턴된 반도체 기판(7)을 반응로(1)의 고주파 전극(2) 위에 놓고 플라즈마 장치로 로터리 펌프를 가동시켜 반응로(1)를 진공상태로 만든후, 전원을 인가하고, 반응가스를 주입하여 반도체 기판(7)상에 산화막(8)을 증착한다.The patterned semiconductor substrate 7 is placed on the high frequency electrode 2 of the reactor 1 and a rotary pump is operated by a plasma apparatus to make the reactor 1 in a vacuum state, and then a power is applied to inject the reaction gas. The oxide film 8 is deposited on the semiconductor substrate 7.
이때, 코에니그(Koening)와 마셀(Maissel) 관계(B. chapman, Glow Discharge Process, (John Wiley & Son's, N. Y., 1980. P156-171)에 의해 면적비의 4승에 반비례하는 자기인가전압(Self-bias voltage)이 형성된다. 즉At this time, the self-applied voltage is inversely proportional to the fourth power of the area ratio by the Koening and the Massel relationship (B. chapman, Glow Discharge Process, (John Wiley & Son's, NY, 1980. P156-171)). Self-bias voltage is formed
여기서 Ve, Vg는 고주파 전극(2)과 접지전극(3)에서 형성된 자기인가전압을 나타내고, Ae와 Ag는 각 전극의 유효면적이다. 즉, 본 발명에서는 노출되는 고주파 전극(2)의 면적을 작게하므로서 화학 기상 반응이 진행되는 기판에 고주파 불꽃방전에 의해 주입가스에서 분리되어 가속된 양이온 +이 자기인가전압에 의해 가속되어 반도체 기판(7) 표면에 충돌한다.Here, Ve and Vg represent self-applied voltages formed at the high frequency electrode 2 and the ground electrode 3, and Ae and Ag are effective areas of each electrode. That is, in the present invention, the cation + accelerated by the self-applied voltage is accelerated by the self-applied voltage by the high-frequency electrode 2 to reduce the area of the exposed high-frequency electrode 2 to the substrate where the chemical vapor reaction proceeds. 7) Hit the surface.
이와 같은 이온 충돌이 기판에서 진행되는 반응을 제3도를 참고하여 설명하면 다음과 같다. 이온 + 충돌이 반도체 기판(7) 표면에서 진행되면 흡착된 종자(species)(a)의 표면 이동도를 증가시키고, 화학 반응을 촉진(b)시켜 불완전한 결합이나 불순물을 제거(또는 탈착)(c)시키며 증착될 산화막(8)의 밀도를 증가(d)시킨다.The reaction in which such an ion collision proceeds on the substrate is described with reference to FIG. 3 as follows. As the ion + collision proceeds on the surface of the semiconductor substrate 7, the surface mobility of the adsorbed seeds (a) is increased and the chemical reaction is promoted (b) to remove (or desorb) incomplete bonds or impurities (c). The density of the oxide film 8 to be deposited is increased (d).
이상과 같이 이온 충돌 효과를 이용하여 기판을 가열하지 않은 저온에서도 실리콘 산화막을 증착할 수 있다.As described above, the silicon oxide film can be deposited even at a low temperature without heating the substrate by using the ion collision effect.
이하에서, 본 발명의 실시예를 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
PECVD장치의 고주파 전극(2)를 측면 및 상부 테두리 부분에 접지된 차폐막(4)을 설치하고, 패턴된 반도체 기판(7)을 고주파 전극(2) 위에 장착하고 로터리 펌프를 가동시켜 반응로(1)의 압력을 0.5토르(Torr)까지 진공상태를 만든 다음, 반응로(1)에 딜루트(dilute)가스로서 질소를 150SCCM, 반응가스로서 산소 38SCCM, 운반질소 7.7SCCM을 주입하고, 고주파 전극(2)에 10∼125W의 전력을 가하여 산화막 형성공정을 진행한다. 이때 산소를 주입하기 위한 TEOS(Terta-ethyl-ortho-silicate) 버블러 온도는 55℃로 한다.A shielding film 4 having a high frequency electrode 2 of the PECVD apparatus grounded at side and upper edge portions is provided, the patterned semiconductor substrate 7 is mounted on the high frequency electrode 2, and a rotary pump is operated to operate the reactor 1 After vacuuming up to 0.5 Torr, nitrogen is injected into the reactor (1) with 150 SCCM of nitrogen as a dilute gas, 38 SCCM of oxygen as a reaction gas, and 7.7 SCCM of carrier nitrogen. 2) is supplied with an electric power of 10 to 125 W to proceed with the oxide film forming process. At this time, TEOS (Terta-ethyl-ortho-silicate) bubbler temperature to inject oxygen is set to 55 ℃.
제4도는 본 발명에 의해 얻어진 산화막 형성상태를 나타낸 단면도로써, 단차의 아래 구석 부분이 종래의 기술과는 달리 두껍게 형성된다.4 is a cross-sectional view showing the oxide film formation state obtained by the present invention, wherein the lower corner portion of the step is formed thicker than in the prior art.
제5도는 증착조건에 따른 산화막의 증착속도와 굴절율의 변화를 나타낸 도표로서, 125W의 고주파 전력에서 11nm, 25W의 고주파 전력에서 15nm, 50W의 고주파 전력에서 16nm, 10W의 고주파 전력에서 14nm, 125W에서 12.5nm의 증착율을 나타내 전력증가에 의해 75W에서 최고의 증착율을 나타냈고 100W 이상에서는 증착율이 서서히 감소함을 보였다. 또한, 증착된 산화막의 반사율은 12.5W에서 1.5 정도에서부터 전력증가에 따라 증가하였으나, 큰 변화는 보이지 않았다.5 is a graph showing the deposition rate and refractive index change of the oxide film according to the deposition conditions, 11nm at 125W high frequency power, 15nm at 25W high frequency power, 16nm at 50W high frequency power, 14nm at 10W high frequency power, 125W The deposition rate of 12.5nm showed the highest deposition rate at 75W due to the power increase, and the deposition rate gradually decreased above 100W. In addition, the reflectance of the deposited oxide film increased with increasing power from about 1.5 at 12.5W, but no significant change was observed.
제6도에 증착 조건에 따른 증착 박막의 IR(Irradiation) 스펙트럼을 나타낸 것으로 전송율이 고주파 전력 10W∼125W의 범위에서 공히 파동수가 1075Cm-1에서 피크를 나타냈다.FIG. 6 shows an IR (Irradiation) spectrum of the deposited thin film according to the deposition conditions, and the wave number peaked at 1075Cm −1 in the range of the high frequency power of 10W to 125W.
이와 같은 본 발명은 이온 충돌 효과를 이용하여 기판을 가열하지 않은 저온에서도 실리콘 산화막을 증착할 수 있고, 표면 이동도가 증가하므로 단차 아래면 구석에 증착되는 산화막의 두께가 두껍게 형성되는 효과가 있다.As described above, the present invention can deposit a silicon oxide film even at a low temperature without heating the substrate by using the ion collision effect, and because the surface mobility is increased, the thickness of the oxide film deposited at the corner of the lower surface of the step is increased.
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| KR1019930016028A KR960014955B1 (en) | 1993-08-18 | 1993-08-18 | Oxide layer deposition method |
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| KR1019930016028A KR960014955B1 (en) | 1993-08-18 | 1993-08-18 | Oxide layer deposition method |
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