KR960013946B1 - Non-volatile semiconductor memory - Google Patents
Non-volatile semiconductor memory Download PDFInfo
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- KR960013946B1 KR960013946B1 KR1019930013480A KR930013480A KR960013946B1 KR 960013946 B1 KR960013946 B1 KR 960013946B1 KR 1019930013480 A KR1019930013480 A KR 1019930013480A KR 930013480 A KR930013480 A KR 930013480A KR 960013946 B1 KR960013946 B1 KR 960013946B1
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- Prior art keywords
- forming
- polysilicon layer
- oxide film
- polysilicon
- floating gate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 230000005641 tunneling Effects 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 241000238631 Hexapoda Species 0.000 claims 1
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 abstract 3
- 229920001296 polysiloxane Polymers 0.000 abstract 2
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000015654 memory Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Abstract
Description
제1도는 종래의 불휘발성 반도체 메모리 구조도.1 is a structure diagram of a conventional nonvolatile semiconductor memory.
제2도는 본 발명의 불휘발성 반도체 메모리의 제조방법을 도시한 공정순서도.2 is a process flowchart showing the manufacturing method of the nonvolatile semiconductor memory of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 터널링 산화막1: silicon substrate 2: tunneling oxide film
3 : 플로팅게이트 4 : 절연막3: floating gate 4: insulating film
5 : 컨트롤게이트 6 : 소오스5: control gate 6: source
7 : 드레인 9 : CVD산화막7: drain 9: CVD oxide film
10 : HSG폴리실리콘10: HSG Polysilicon
본 발명은 불휘발성 반도체 메모리 제조방법에 관한 것으로, 특히 정전용량 커플링비(Capscitive coupling ratio)를 증가시키기 위해 플로팅(Floating gate)의 표면의 유효면적을 증가시키는 공정에 관한 것이다.The present invention relates to a method of manufacturing a nonvolatile semiconductor memory, and more particularly, to a process of increasing the effective area of a surface of a floating gate to increase a capacitive coupling ratio.
종래의 대부분의 EEPROM, EPROM, 플래쉬 메모리등과 같은 불휘발성 반도체 메모리는 제1도에 도시한 바와 같이 플로팅게이트(3)와 컨트롤게이트(5)의 2개의 폴리실리콘층을 가지는 트랜지스터로 구성된다.Most conventional nonvolatile semiconductor memories such as EEPROM, EPROM, flash memory and the like are composed of transistors having two polysilicon layers, a floating gate 3 and a control gate 5, as shown in FIG.
이때 플로팅게이트(3)에 걸리는 전압은 컨트롤게이트(5)에 걸리는 전압과 정전용량 커플링비의 곱으로 나타난다.The voltage across the floating gate 3 is represented by the product of the voltage across the control gate 5 and the capacitance coupling ratio.
이와 같은 메모리를 프로그램할 때 매우 높은 전압(예:12V,25V)이 컨트롤게이트에 가해져야만 그중 정전용량 커플링비만큼의 전압이 플로팅게이트에 가해진다. 이와 같이 높은 전압이 필요하기 때문에 외부회로의 스케일링(scaling)에 많은 문제가 있다.When programming such a memory, a very high voltage (eg 12V, 25V) must be applied to the control gate, of which the voltage equal to the capacitance coupling ratio is applied to the floating gate. As such a high voltage is required, there are many problems in scaling of an external circuit.
정전총량 커플링비(k)는 다음식으로 나타낼 수 있다.The total capacitance coupling ratio k can be expressed by the following equation.
여기서, C1,C2…C5는 각각 제1도에 나나낸 바와 같다.Where C 1 , C 2 . C 5 is as shown in FIG. 1, respectively.
즉 C1은 컨트롤게이트(5)와 플로팅게이팅(3) 사이의 커패시턴스, C2는 플로팅게이드(3)와 소오스(6) 사이의 터패시턴스, C3는 플로팅게이트(3)와 드레인(7) 사이의 커패시턴스, C4는 플로팅게이트(3)와 채널 사이의 커패시턴스, C5는 플로팅게이트(3)와 기판(1) 사이의 커패시턴스를 각각 나타낸다.In other words, C 1 is the capacitance between the control gate (5) and the floating gate (3), C 2 is the capacitance between the floating gate (3) and the source (6), C 3 is the floating gate (3) and drain (7) ) capacitance between, 4 C is the capacitance, C 5 between the floating gate 3 and the channel are respectively the capacitance between the floating gate 3 and the substrate 1.
한편, 플로팅게이트에 걸리는 전압 Vf는On the other hand, the voltage V f across the floating gate is
Vf=K·VgV f = K
(K:정전용량 커플링비, Vg:컨트롤게이트에 걸리는 전압)으로 나타낼 수 있는바, 플로팅게이트에 가해진 전압은 컨트롤게이트에 가해진 전압의 일부분이 되므로 상당히 높은 전압이 컨트롤게이트에 가해져야 프로그램(Program)과 소거(erase) 동작이 가능하게 된다.It can be expressed as (K: capacitance coupling ratio, Vg: voltage across the control gate). Since the voltage applied to the floating gate becomes part of the voltage applied to the control gate, a very high voltage must be applied to the control gate. And erase operation is possible.
즉, 컨트롤게이트에 높은 전압을 인가하면 상당한 전압이 컨트롤게이트와 플로팅게이트 사이의 절연체(4)에 걸리고, 그중 일부분은 플로팅게이트(3)와 기판(1) 사이에 걸리게 된다.In other words, when a high voltage is applied to the control gate, a significant voltage is applied to the insulator 4 between the control gate and the floating gate, and a part of the voltage is applied between the floating gate 3 and the substrate 1.
이에 커패시던스가 클수록 작은 전압이 걸리게 된다.The larger the capacitance, the smaller the voltage.
따라서 플로팅게이트와 기판 사이에 필요한 전압을 상대적으로 낮은 전압에서 얻기 위해서는 플로팅게이트와 컨트롤게이트 사이의 커패시턴스값을 증가시키는 것이 요구된다.Therefore, in order to obtain the required voltage between the floating gate and the substrate at a relatively low voltage, it is required to increase the capacitance value between the floating gate and the control gate.
본 발명은 상술한 문제를 해결하기 위한 것으로, 정전용량 커플링비를 증가시키기 위해 플로팅게이트의 표면 유효면적을 증가시키는 방법을 제공하는 것을 그 목적으로 한다. 상기 목적을 달성하기 위해 본 발명의 불휘발성 반도체 메모리 제조방법은 실리콘기판상에 터널링 산화막을 형성하는 공정과, 상기 터널링 산화막위에 표면에 요철이 있는 제1폴리실리콘층을 형성하는 공정, 상기 제1폴리실리콘층표면에 절연막을 형성하는 공정, 상기 절연막상에 제2폴리실리콘층을 형성하는 공정, 상기 터널링 산화막, 제1폴리실리콘층, 절연막 및 제2폴리실리콘층을 소정패턴으로 패터닝하는 공정, 및 이온주입에 의해 실리콘기판(1)에 소오스(6) 및 드레인(7)을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.The present invention has been made to solve the above problem, and an object thereof is to provide a method for increasing the surface effective area of the floating gate to increase the capacitance coupling ratio. In order to achieve the above object, a nonvolatile semiconductor memory manufacturing method of the present invention comprises the steps of forming a tunneling oxide film on a silicon substrate, and forming a first polysilicon layer having irregularities on the surface on the tunneling oxide film, the first Forming an insulating film on the surface of the polysilicon layer, forming a second polysilicon layer on the insulating film, patterning the tunneling oxide film, the first polysilicon layer, the insulating film, and the second polysilicon layer in a predetermined pattern; And forming a source (6) and a drain (7) on the silicon substrate (1) by ion implantation.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명의 불휘발성 반도체 메모리 제조방법을 도시하였다.2 illustrates a method of manufacturing a nonvolatile semiconductor memory of the present invention.
먼저, (a)와 같이 실리콘기판(1)상에 터널링(Tunneling) 산화막(2)을 형성하고 계속해서 제1폴리실리콘층(3)과 얇은 CVD(Chemical Vapor Deposition)산화막(9)을 형성하고 그 위에 HSG(Hemispherical Grain)폴리실리콘(10)을 580∼595℃ 온도로 0.2∼0.5torr 압력하에서 얇게 증착한다.First, a tunneling oxide film 2 is formed on the silicon substrate 1 as shown in (a), and then a first polysilicon layer 3 and a thin chemical vapor deposition (CVD) oxide film 9 are formed. Hemispherical Grain (HSG) polysilicon 10 is thinly deposited thereon at a temperature of 580 to 595 ° C. under a pressure of 0.2 to 0.5 torr.
다음에 (b)와 같이 상기 HSG폴리실리콘(10)을 가볍게 식각(slightly etch)하고 이에 따라 노출되는 CVD산화막(9)을 (c)와 같이 남아 있는 HSG폴리실리콘(10)을 마스크로 이용하여 식각한 후, HSG폴리실리콘을 제거하고 (d)와 같이 상기 CVD산화막(9)을 마스크로 하여 제1폴리실리콘층(3)을 식각함으로써 폴리실리콘층의 표면에 요철을 형성한다.Next, the HSG polysilicon 10 is lightly etched as shown in (b), and the exposed CVD oxide film 9 is thus used as a mask using the remaining HSG polysilicon 10 as shown in (c). After etching, the HSG polysilicon is removed and the first polysilicon layer 3 is etched using the CVD oxide film 9 as a mask as in (d) to form irregularities on the surface of the polysilicon layer.
이어서 (e)와 같이 상기 표면에 요철이 형성된 제1폴리실리콘층(3)상에 절연막(4)으로서 ONO(Oxide/Nitride/Oxide)막을 형성하고 이 위에 제2폴리실리콘층(5)을 형성한다.Subsequently, an ONO (Oxide / Nitride / Oxide) film is formed as an insulating film 4 on the first polysilicon layer 3 having irregularities on the surface as shown in (e), and the second polysilicon layer 5 is formed thereon. do.
다음에 (f)와 같이 터널링 산화막(2), 제1폴리실리콘층(3), ONO막(4), 제2폴리실리콘층(5)의 적층구조물을 소정패턴으로 패터닝하여 제1폴리실리콘층으로 된 플로팅게이트(3)과 컨트롤게이트(5)를 형성한 후, 이온주입공정을 실시하여 소오스(6) 및 드레인(7)을 형성한다.Next, as shown in (f), the laminated structure of the tunneling oxide film 2, the first polysilicon layer 3, the ONO film 4, and the second polysilicon layer 5 is patterned in a predetermined pattern to form the first polysilicon layer. After the floating gate 3 and the control gate 5 are formed, an ion implantation process is performed to form the source 6 and the drain 7.
이와 같이 플로팅게이트를 표면에 요철이 형성된 폴리실리콘으로 형성하며 플로팅게이트의 유효면적을 증가시킴으로써 플로팅게이트와 컨트롤게이트간의 커패시턴스를 증가시킨다.As such, the floating gate is formed of polysilicon having irregularities formed on the surface thereof, and the capacitance between the floating gate and the control gate is increased by increasing the effective area of the floating gate.
예컨대, 커패시터의 높이를 0.3μm로 형성할 경우 상기 본 발명에 의하면 약 2.5배의 면적증가 효과가 있으므로 커패시턴스가 2.5배 증가한다.For example, when the height of the capacitor is 0.3 μm, the capacitance increases by about 2.5 times according to the present invention, which increases the capacitance by 2.5 times.
기존소자의 커플링비가 0.4정도라면 본 발명의 방법을 사용하게 되면If the coupling ratio of the existing device is about 0.4,
K가 0.625로 증가하므로 기존소자의 프로그램시 필요한 전압이 12V라면 본 발명에 의하면 7.7V로 프로그램이 가능하게 된다.Since K increases to 0.625, if the required voltage for programming the existing device is 12V, the present invention can be programmed to 7.7V.
이상 상술한 바와 같이 본 발명에 의하면, 플로팅게이트와 컨트롤게이트 사이의 커패시턴스 값의 증가로 인하여 커플링비가 증가하며 이에 따라 낮은 게이트 전압에서도 프로그램 및 소거동작이 가능하게 되어 외부회로의 스케일링이 가능해진다.As described above, according to the present invention, the coupling ratio increases due to an increase in the capacitance value between the floating gate and the control gate, thereby enabling programming and erasing operation even at a low gate voltage, thereby enabling scaling of an external circuit.
또한 종래와 동일한 게이트 전압이 가해질 경우에는 리드전류(read current)가 증가하게 되므로 억세스(accse)시간이 감소되는 효과가 있다.In addition, when the same gate voltage is applied as in the related art, a read current increases, thereby reducing an access time.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013480A KR960013946B1 (en) | 1993-07-16 | 1993-07-16 | Non-volatile semiconductor memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930013480A KR960013946B1 (en) | 1993-07-16 | 1993-07-16 | Non-volatile semiconductor memory |
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| KR950004607A KR950004607A (en) | 1995-02-18 |
| KR960013946B1 true KR960013946B1 (en) | 1996-10-10 |
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| KR100808800B1 (en) * | 2006-08-31 | 2008-02-29 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method thereof |
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| KR100416816B1 (en) * | 1996-12-30 | 2004-04-06 | 주식회사 하이닉스반도체 | Method for forming floating gate of semiconductor device |
| KR20000026228A (en) * | 1998-10-19 | 2000-05-15 | 김영환 | Flash memory cell and manufacturing method for the same |
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1993
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100808800B1 (en) * | 2006-08-31 | 2008-02-29 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabrication method thereof |
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| KR950004607A (en) | 1995-02-18 |
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