KR960013047B1 - Electronic delay circuit for firing ignition element - Google Patents

Abstract

No content

Description

Electronic delay circuit to ignite the ignition element of the electric blasting machine

1 is a schematic block diagram illustrating the principle of a prior art electronic delay circuit for use in an initiator.

2 shows waveforms at various parts of FIG. 1;

3 is a block diagram showing an embodiment of an electronic delay circuit for igniting an ignition element according to the present invention.

4A is a circuit diagram showing the preset of FIG.

4B is a circuit diagram showing the clocked inverter of FIG.

5 is a block diagram showing waveforms in various parts of FIG.

6A and 6B show a comparison of the waveforms of the prior art shown in FIG. 1 with the embodiment shown in FIG.

7 is a longitudinal cross-sectional view of an atomization fuse in accordance with an embodiment of the present invention.

8A and 8B show the configuration of parts attached to the detonator.

* Explanation of symbols for main parts of the drawings

1: electric blasting machine 5: counting circuit

8: ignition circuit 50; Main counter

52: frequency divider 60: preset circuit

70: over-excitation circuit 90: oscillator

The present invention relates to an electronic delay circuit for storing an electrical energy supplied from an electric blasting device and for igniting an ignition element which correctly ignites the detonator after a predetermined delay time.

A structure similar to that of a multi-stage blasting system is described in Japanese Patent Application Laid-Open No. 285800/1989 to minimize ground blasting effects. This application teaches the accuracy of the delay intervals for sequentially igniting the detonator in order to reduce ground oscillation. According to the above application, the delay time interval t and the standard deviation sigma of the delay time interval t satisfy the following relationship.

t / σ ≧ 10 … … … … … … … … (One)

This application describes that ground oscillation cannot be reduced unless the above conditions are met.

As a result, in order to set the delay time interval for ignition of the initiator to 10 ms, the standard deviation of the delay time must be equal to or less than one. Similarly, a 5 ms delay time interval requires less than 0.5 ms standard deviation.

Japanese Patent Laid-Open No. 53479/1988 discloses an electric detonator ignited by an electronic delay circuit. This circuit accepts only electrical energy through the lead wire and activates a digital timer, including a crystal or ceramic oscillator, to ignite the electrical detonator after a predetermined delay time. However, the above application does not suggest a technique that satisfies the condition of Equation (1).

U.S. Patent No. 4,445,435 / 1984 discloses a means for storing electrical energy, an oscillator circuit using a crystal or ceramic oscillator, a counter reset circuit for resetting the counter and the counter, and an ignition of the electrical detonator after a predetermined delay time. Teaching an electronic delay blasting circuit comprising means.

Likewise, European Patent Application Publication No. 261,886 discloses a delay circuit for electrical ignition of a detonator.

1 and 2 illustrate the principle of the delay circuit disclosed in the European patent application. In this figure, the electro blasting apparatus (electric blasting apparatus) 1 supplies a voltage (electrical energy) as shown in Fig. 2A. The electrical energy is supplied to the operating circuit 2, the capacitor 3, the clock pulse generator 4 and the counting circuit 5 via the wire 6, and as shown in FIG. 3) are stored. The operation circuit 2 maintains the reset state of the counter circuit 5 for the counter reset time T (= 200 to 300 ms), and counts the counter when the counter reset time T elapses after the application of the input voltage is started. Activate the counting circuit 5 to begin. The time T is defined by the falling edge of the input voltage as shown in Figures 2 (a) and (c). This is because the output frequency of the crystal or ceramic oscillator included in the clock pulse generator 4 is stabilized after the counter reset time T as shown in Fig. 2C. The counting circuit 5 counts the pulses of the pulse train generated by the clock pulse generator 4 and switches as shown in FIG. 2D so that current is supplied from the capacitor 3 to the ignition circuit 8. Trigger the circuit (7). Thus, the electric detonator is ignited after a predetermined delay time as shown in Fig. 2E.

The crystal or ceramic oscillator used by the clock pulse generator 4 has a problem that it takes about 200 to 300 ms until the oscillator becomes a steady state oscillator. That is, the output frequency of the oscillator is unstable during the counter reset time T. Therefore, the prior art cannot start the pulse count of the pulse train output from the oscillator until the counter reset time T has elapsed.

The long counter reset time T has a problem that the delay time becomes unstable. There are two main reasons for this.

First, as the counter reset time increases, the probability that the input voltage can be affected by external noise during the counter reset time T, as shown in FIG. The probability that this external noise can be affected by the input voltage increases. This external noise can change the falling edge of the input voltage, which changes the start time of the counting circuit 5. This is a big problem because severe noise is generated by incomplete contact of the lead wire or by switching of an electric blasting machine at the blasting position. In order to remedy this problem, the actuation circuit 2 becomes complicated so that an increase in the size and cost of the actuation circuit is inevitable.

Second, if the counter reset time is increased, the error in the counter reset time will increase because the counter reset time is regulated by the analog voltage. Also, longer counter reset times will increase power consumption.

Since the reset signal for ignition of the detonator is generated by detecting the rising or falling edge of the electrical signal from the blasting device of the prior art, it is difficult to blast at the correct timing when a plurality of in series detonators are in operation. .

Therefore, it is an object of the present invention to provide an electronic delay circuit for igniting an ignition element that can improve the accuracy of the delay time for igniting the initiator.

Another object of the present invention is to provide an electronic delay circuit for igniting an ignition element that can reduce power consumption during operation of a timer circuit.

According to the present invention, an electronic delay circuit for igniting an ignition element comprises: means for storing electrical energy supplied from an electrical blasting device, means for oscillating a clock pulse train using electrical energy stored in said storage means, said oscillation Means for over-stimulating means, means for counting clock pulses of the clock pulse train, means for generating a trigger signal when the counting means counts a predetermined number of clock pulses in the clock pulse train and the trigger signal Means for discharging electrical energy stored in said storage means in response to said ignition element.

The overexcited circuit means comprises means for supplying current from the storage means to the oscillating means for a first time period after electrical energy is supplied.

According to another feature of the invention, the electronic delay circuit for igniting the ignition element further comprises means for maintaining the reset state of the counting means for a second predetermined time period after electrical energy is supplied, wherein the reset The state maintaining means releases the reset state when the second predetermined time period ends so that the counting means starts counting.

The reset state maintaining means also includes the time constant circuit and a comparator, the time constant circuit includes a capacitor and a resistor, and the comparator compares a predetermined reference voltage with a voltage across the capacitor.

The second selection time period of the reset state maintaining means may be equal to or less than 5 ms.

The electronic delay circuit for igniting the ignition element of the present invention further comprises a discharge means connected in parallel with the storage means to promote the discharge of the electrical energy stored in the storage means.

In the electronic delay circuit of the present invention for igniting the ignition element, the counting means may be a preset counter whose initial value is set by cutting off the preset wire.

The electronic delay circuit of the present invention for igniting an ignition element further comprises means for presetting an initial value of the preset counter, wherein the presetting means is configured to reset the preset from the storage means after the presetting of the initial value is completed. Means for separating the setting means.

The electronic delay circuit of the present invention for igniting an ignition element further comprises a resistor connected between the wires carrying the electrical energy input to the storage means.

According to another feature of the invention, an electronic delay circuit for igniting an ignition element comprises means for storing electrical energy supplied from an electrical blasting device, means for oscillating a clock pulse train using the electrical energy stored in said storage means. And counting clock pulses of the clock of the counting means for a second predetermined time period after the electrical energy is supplied using the electrical energy stored in the storage means, and the second selecting time period is configured such that the counting means starts counting. Reset state holding means for releasing said reset state upon termination, means for generating a trigger signal when said counting means counts a predetermined number of said clock pulses in said clock pulse train and said storage in response to said trigger signal Means for discharging electrical energy stored in the means to the ignition element. .

The electronic delay circuit for igniting an ignition element further comprises means for over exciting the oscillating means, wherein the over excited means draws current from the storage means to the oscillating means for a first time period after electrical energy is supplied. Means for supplying.

The means includes a time constant circuit and a comparator, wherein the time constant circuit comprises a capacitor and a resistor, and the comparator compares the voltage across the capacitor with a predetermined reference voltage.

The second selection time period of the reset state maintaining means may be equal to or less than 5 ms.

The electronic delay circuit of the present invention for igniting an ignition element further includes discharge means connected in parallel with the storage means for promoting discharge of the electrical energy stored in the storage means.

The counting means is a preset counter whose initial value is set by cutting off the preset wire.

The electronic delay circuit of the present invention for igniting an ignition element further comprises means for presetting an initial value of the preset counter, wherein the presetting means is configured to reset the preset value from the storage means after the presetting of the initial value is completed. Means for separating the setting means.

The electronic delay circuit of the present invention for igniting an ignition element also includes a resistor connected between the wires carrying the electrical energy input to the storage means.

In the present invention, the electronic delay circuit, the oscillating means, the counting means, the overexcited means and the reset state maintaining means for igniting the ignition element are integrated in one IC chip.

According to the invention, the output frequency of the oscillation means reaches a steady state frequency in a very short time due to overexcitation. As a result, the accuracy of the delay time for igniting the initiator is improved. In addition, since the counting means starts counting after the output frequency has reached a steady state, a high precision and reliable delay time can be obtained.

Furthermore, the short oscillation rise time reduces the power consumption of the oscillator. As a result, it is possible to reduce the size of a capacitor that stores electrical energy. This makes it possible to provide an easy-to-use detonator.

In the present invention, the counter reset time is generated inside the delay circuit. Therefore, unlike the prior art, the detection of an external signal for controlling the counter reset time becomes unnecessary. Therefore, a highly reliable electronic initiator can be obtained.

The counter reset time is set at about the same time as the time at which the output frequency of the oscillation means reaches a steady state. Since the counter reset time in the present invention is very short, a simple circuit comprising a capacitor and a resistor can achieve a counter reset time that is satisfactorily satisfactory. This saves the cost of the circuit.

The above description and other objects, effects, features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

The present invention will now be described with reference to the accompanying drawings.

3 is a block diagram showing an embodiment according to the present invention.

In this figure, the input terminals 11 and 12 are connected to the electric blasting apparatus 1 of FIG. 1 via the wire 6. The resistor 13 and the rectifier 14 are connected between the input terminals 11 and 12. The capacitor 15 and the resistor 16 are connected between the output terminals of the rectifier 14. The resistor 13 prevents charging of the capacitor 15 to a voltage at which stray currents, which often occur at blasting sites, can ignite the initiator. Furthermore, the resistor 13 acts as a voltage divider when multiple initiators are connected in series in a multi-stage blasting system such that approximately the same voltage is supplied to each rectifier 14. Rectifier 14 allows capacitor 15 to be charged in one direction regardless of the polarity of the input voltage supplied to terminals 11 and 12. In the present embodiment, the resistance of the resistor 13 is 15 Ω, and the capacity of the capacitor 15 is 1,000 kΩ. In this case, the capacitor 15 is charged to a maximum voltage of 15V over 5 to 10 ms by the electric energy supplied from the electric blast device 1.

The series circuit of the thyristor (switching device) 17 and the ignition resistor (bridge wire) 18 are connected across the capacitor 15. In addition, the input terminal of the constant voltage circuit 19 is connected across the capacitor 15. The series circuit of the capacitor 20 and the resistor 21 and the capacitor 22 is connected in parallel across the output terminal of the constant voltage circuit 19. The resistor 21 and the capacitor 22 constitute a counter reset time circuit 23. The digital timer 30 is also connected to the output terminal of the constant voltage circuit 19.

The digital timer 30 includes a reset circuit 40, a main counter 50 for counting a delay time for ignition of the initiator, a preset circuit 60 for presetting an initial value of the main counter 50, an oscillator And an overexcited circuit 70 which over-excites the oscillator 90 such that 90 is in a steady state within a very short time.

The reset circuit 40 includes a voltage divider consisting of a comparator 42 and resistors 44 and 46. The inverting input terminal of the comparator 42 is connected to the connection point of the resistor 21 and the capacitor 22, and the non-inverting input terminal of the comparator 42 is connected to the connection point of the resistor 44 and 46. Therefore, the output of the comparator 42 changes from the high level to the low level after the selection time T1 defined by the time constants of the resistor 21 and the capacitor 22. The selection time T1 is designated, for example, 5 ms corresponding to the counter reset time of the present invention.

The main counter 50 is a 13-bit preset type counter to which the pulse string Sf is supplied from the frequency divider 52. Frequency divider 52 is a 12-bit divider. Therefore, the output frequency of the divider 52 is 1/4096 of the clock pulse string Se frequency supplied from the oscillator 90.

The main counter 50 is connected to the circuit 60 which presets the initial value of the main counter 50. The preset circuit 60 is operated by the flip flop 56. Flip flop 56 is set by the rising edge of signal SR. On the other hand, the main counter 50 and the frequency divider 52 are reset by the falling edge of the signal SR.

4A shows a preset circuit 60 including a number of switching circuits 62. Each switching circuit 60 includes a p-channel FET 64 and an n-channel FET 66 connected in series via a resistor 67. The gates of the two FETs are connected to the Q output of flip flop 56. When the flip flop 56 is set, that is, when the gate voltage is higher than the threshold voltage, the p-channel FET 64 is cut off and the n-channel 66 is conducted. Therefore, the output level of each switching circuit 62 is low, and the preset value of the main counter 50 does not change. Conversely, when the flip flop 56 is in the reset state, that is, when the gate voltage is lower than the threshold voltage, the p-channel FET 64 is inverted and the n-channel FET 66 is shut off. In this case, the output level of each switching circuit 62 is determined by the state of the time set lines 68-1, 68-2, ..., 68-m. The output level of the switching circuit 62 is low when the time set line 68-j is grounded, and high when the time set line 68-j is open.

Referring again to FIG. 3, the output of the main counter 50 is supplied to the flip flop 58 and sets the flip flop 58 that was previously reset by the rising edge of the signal SR. When the flip flop 58 is set, the thyristor 17 is triggered and turned on. Thus, all the electrical energy remaining in the capacitor 15 after the delay circuit has been consumed is supplied to the ignition resistor 18, and the detonator explodes.

Over-excited circuit 70 includes auxiliary counter 72, flip-flops 74-1, 74-2, ..., 74-n, clocked inverters 76-1, 76-2, ..., 76-n And an inverter 78. The counter 72 outputs signals R1, R2, ..., Rn at intervals of 1 mu S, and supplies them to the reset terminals of the flip flops 74-1, 74-2, ..., 74-n, respectively. The flip flops 74-1, 74-2, ..., 74-n are simultaneously set by the rising edge of the signal SR and are sequentially reset by the signals R1, R2, ..., Rn. The output terminal of the flip flop 74-i (i = 1, 2, ..., n) is connected to the control terminal of the clocked inverter 76-i. The excess circuit itself is well known in the field of electronic circuits, as shown in FIG. 9 of Japanese Patent Laid-Open No. 200009/1992.

4B is a circuit diagram of a clocked inverter 76-i. The control terminals 83 and 84 of the clocked inverter 76-i are connected to the output terminal of the flip flop 74-i. The input terminal 81 and output terminal 82 of the clocked inverter 76-i are connected to the oscillator 90. When the high level signal is supplied to the control terminal 83 and the low level signal is supplied to the control terminal 84, the clocked inverter acts as an inverter. On the other hand, when the low level signal is supplied to the control terminal 83 and the high level signal is supplied to the control terminal 84, the clocked inverter is electrically disconnected from the oscillator 90.

Oscillator 90 includes crystal oscillator 92, feedback resistor 94 connected in parallel with crystal oscillator 92, and capacitors 96 and 98 connected between crystal oscillator 92 and ground. The frequency of the crystal oscillator is preferably in the range of 1 MHz to 16 MHz. If the frequency is too low, the rise time of the oscillator becomes long. As a result, the counter reset time T1 increases, adversely affecting the accuracy of the delay time. If the frequency is too high, the power consumption increases. As a result, the capacitor 15 cannot supply enough electrical energy to explode the detonator.

Next, the operation of the delay circuit of FIG. 3 will be described with reference to FIG.

5 shows waveforms at various parts of the delay circuit.

The voltage Sa is applied to the input terminals 11 and 12 from the electric blast device at time t0. The electrical energy provided by the voltage Sa is stored in the capacitor 15, and the voltage Sb across the capacitor 15 increases rapidly. The constant voltage circuit 19 starts to operate at a time t1 (a few mu S) immediately after the application of the voltage Sa, and outputs a constant voltage Sc (for example, Sc = 3.3 V).

The output voltage Sc is applied to the capacitor 22 through the resistor 21, so that the voltage Sd across the capacitor 22 gradually increases. When the voltage Sd exceeds the voltage determined by the voltage divider consisting of resistors 44 and 46 at time t2, the output of the comparator 42 changes its output level from high level to low level, and this change is It becomes the falling edge of the signal SR. Therefore, the falling edge of the signal SR is generated after the time interval T1 (about 5 ms in this embodiment) has passed the time t1. Signal SR sets flip flops 56, and 74-1 through 74-n, and resets flip polls 58 by its rising edge at time t1. At the same time, the signal SR resets the main counter 50, the frequency divider 52 and the counter 72 by its falling edge at time t2.

During time interval T1, crystal oscillator 92 is overcharged by clocked inverters 76-1 through 76-n and inverter 78, and enters a steady state. That is, the frequency of the pulse train output from the crystal oscillator 92 is stabilized during the time interval T1.

At time t2, frequency divider 52 starts operation and outputs a pulse train Sf consisting of pulses having an interval of 1 ms. At the same time, the counter 72 starts counting the clock pulses supplied from the oscillator 90 and generates signals R1 to Rn at intervals of 1 ms. Signal R1 sets flip flop 56 and sets flip flop 74-1 at time t3, which is 1 ms after time t2. Therefore, the signal Sg supplied to the preset circuit 60 rises at time t3 and separates the preset circuit 60 from the constant voltage circuit 19. This reduces the power consumption by the delay circuit.

After the time t3, the flip flops 74-1 to 74-n are sequentially reset at every Tz interval (1 ms) by the signals Sh = R1, R2, ..., Rn. Thus, clocked inverters 76-1 through 76-n are sequentially blocked from oscillator 90. Therefore, overexcitation of the oscillator 90 is gradually released by the signal Sh. As a result, the current Si supplied to the oscillator 90 is supplied by the inverter 78 during steady state excitation at 20 mA supplied from the inverter 76 and the inverter 78 clocked during the overcharge. Gradually change to 0.2mA.

The crystal oscillator 92 consumes substantially more power in the initial oscillation phase, and the power consumption is automatically reduced as the oscillation approaches a steady state. Therefore, since the crystal oscillator 92 is excessively driven (large current driving) by the clocked inverter of constant voltage driving, the crystal oscillator is not damaged (reduces the current value slowly) because it is initially driven with a large current and slowly decreases the current value. ), A stable oscillation state is reached in a very short time.

Using this feature of the crystal oscillator, clocked inverter 76 and inverter 78 can be replaced with an inverter capable of supplying enough current to induce an overexcitation of the crystal oscillator. In this case, clocked inverter 76 and flip flop 74 may be omitted.

When the count value of the main counter 50 reaches the preset value, the main counter 50 sets the flip flop 58. This causes the trigger signal Sj of the thyristor 17, and the current Sk is supplied from the capacitor 15 to the ignition resistor 18. Thus, the detonator explodes.

6A and 6B show the comparison of the characteristics of the present invention and the prior art described above.

The counter reset time T1 of the present invention is much shorter than that of the prior art. For example, the counter reset time T1 of the present invention is about 5 ms while in the prior art it is about 200 to 300 ms. Furthermore, the counter 50 of the present invention is started by the signal SR generated inside the circuit, while the counter of the prior art is started by the input voltage supplied from the electric blasting device 1 through the wire 6. do. As a result, the counter start of the prior art is greatly affected by external noise. On the other hand, the counter disclosure of the present invention is less affected by external noise.

The electrical delay detonator lead can be miniaturized by the use of integrated circuit (IC) technology.

7 and 8A and 8B show the construction inside the detonator according to the present invention. For example, a cylindrical housing 144, a tube shell made of plastic material, covers a delay circuit arranged over the electrical detonator 145 and the printed board 147. The printed board 147 includes the digital timer 30 integrated in the IC chip, the resistors 13a and 13b constituting the resistor 13, the rectifier 14, the thyristor 17, the constant voltage circuit 19, and the capacitor ( 22) and oscillator 92 are received thereon. Digital timers can be well configured using C-MOS technology. A capacitor 15 for storing electrical energy is attached to the printed board 147. The crystal oscillator 92 is fixed to the printed circuit board 147 with a double adhesive tape 148. In addition, the time set wire 68 is formed on the bottom surface of the printed board 147. The housing is sealed with a primer 151, and the leg wires 152 and 153 are guided from the inside of the housing to the outside through the primer 151. The electric detonator includes a base charge 150, a fuse charge 149 and an ignition charge 18 housed in a shell (usually copper) with a plug at one end. Ignition current (ignition energy) is supplied to the ignition resistor (bridge wire) via the leg wire.

According to this configuration, these elements can be constructed in a housing 144 whose outer diameter is up to 17 mm and its length is less than 110 mm. In this case, the capacitor 15 has an outer diameter of up to 10 mm and the total length of the capacitor 15 and the printed board 147 is up to 53 mm.

In this embodiment, a capacitor 20 of 6.2 k? 5% and a resistor of 750 K? 2% were used. In addition, the threshold voltage of the reset terminal of the digital timer 30 is 2.07V ± 5%. The sum of the errors due to these errors is calculated as the mean square. The calculated error sum of the counter reset time T1 is 7.9% or ± 0.4 ms. The timer reset time (T1) was measured on 500 specimens made with the test initiator fuse, which is in the range of 4.7 ± 0.2 ms.

The precision of the crystal oscillator 92 is 30 ppm. Thus, when the delay time is set to 8 seconds, the error due to the crystal oscillator 92 is about 0.20 ms. In the case where the total error of the counter reset time T1 is 0.4 ms, the total error is 0.6 ms. Therefore, a precision better than ± 1 ms can be achieved.

According to the embodiment, since the counter reset time T1 is much shorter than that of the prior art, high precision of the resistor 21 and the capacitor 22 is not required. Therefore, inexpensive resistor and capacitors can be used to construct inexpensive counter reset time circuit 23.

The digital timer 30 with no lead frame attached prior to packaging can be used in place of the packaged IC digital timer. In this case, the size of the delay circuit will be further reduced.

The oscillator 92 may be replaced with a thinner chip type oscillator than the oscillator 92 shown in FIG. 8A.

Furthermore, all elements except the capacitors 15, 20, 96 and 98 can be integrated in one IC chip. This will make the delay circuit more compact.

DETAILED DESCRIPTION The present invention will be described in detail with respect to various embodiments, and variations and modifications without departing from the broad scope of the invention will become apparent from the detailed description given above by those skilled in the art. Therefore, it is intended that the appended claims cover all such modifications and variations as fall within the true scope of the invention.

Claims (24)

Means 15 for storing electrical energy supplied from an electric blasting machine, means for oscillating a clock pulse train using the electrical energy stored in said storage means 90; 92, 78, 94, 96 (98), means for over-exciting the oscillating means (70; 72, 74-1, 74-2, ..., 74-n, 76-1, 76-2, ..., 76 n), means (50, 52) for counting clock pulses of said clock pulse sequence, and means (58) for generating a trigger signal when said counting means counts a predetermined number of said clock pulses of said clock pulse sequence; And means (17) for discharging electrical energy stored in said storage means to said ignition element in response to said trigger signal. The method according to claim 1, wherein said over-excited means (70) comprises means for supplying a current from said storage means (15) to said oscillation means (90) for a first time period after said electrical energy has been supplied. An electronic delay circuit for igniting an ignition element. Further comprising means for maintaining the reset state of the counting means (50, 52) for a second predetermined time period after electrical energy has been supplied, wherein said reset state maintaining means (40; 42) 44 and 46 release the reset state when the second predetermined time period ends so that the counting means 50 and 52 start counting. Circuit. 4. The reset state maintaining means (40) comprises a time constant circuit and a comparator (42), the time constant circuit comprising a capacitor (22) and a resistor (21), and the comparator (42). ) Is an electronic delay circuit for igniting an ignition element, characterized in that the voltage across the capacitor is compared with a predetermined reference voltage. 4. The electronic delay circuit according to claim 3, wherein said second selection time period of said reset state maintaining means (40) is equal to or shorter than 5 ms. An ignition element according to claim 1, further comprising a discharge means (17) connected in parallel with said storage means (15) in order to promote the discharge of said electrical energy stored in said storage means (15). Electronic delay circuit for igniting the lamp. 4. An ignition element according to claim 3, further comprising a discharge means (17) connected in parallel with said storage means (15) in order to promote the discharge of said electrical energy stored in said storage means (15). Electronic delay circuit for igniting the lamp. The electronic delay circuit for igniting an ignition element according to claim 1, wherein said counting means (50, 52) is a preset counter whose initial value is set by interrupting a preset wire. 4. An electronic delay circuit for igniting an ignition element according to claim 3, wherein said counting means (50, 52) is a preset counter whose initial value is set by interrupting a preset wire. 9. The apparatus of claim 8, further comprising means for presetting an initial value of the preset counter, wherein the presetting means means for separating the presetting means from the storage means after the presetting of the initial value is completed. Electronic delay circuit for igniting an ignition element comprising a. 10. The apparatus of claim 9, further comprising means for presetting an initial value of the preset counter, wherein the presetting means separates the presetting means from the storage means 15 after the presetting of the initial value is completed. An electronic delay circuit for igniting an ignition element, comprising means for. The electronic delay circuit according to claim 1, further comprising a resistor connected between the wires carrying the electrical energy input to said storage means (15). 4. An electronic delay circuit for igniting an ignition element as claimed in claim 3 further comprising a resistor connected between the wires carrying the electrical energy input to said storage means (15). The electronic delay circuit for igniting an ignition element according to claim 1, wherein said oscillation means (90), counting means (50, 52) and over-excitation means (70) are integrated in one IC chip. 4. An ignition element according to claim 3, wherein said oscillation means (90), counting means (50, 52), over-excitation means (70), and reset state maintaining means (40) are integrated in one IC chip. Electronic delay circuit for igniting the lamp. Means for storing electrical energy supplied from an electric blasting machine (15), means for oscillating a clock pulse train using electrical energy stored in said storage means (90; 78,92,94,96) 98, counting the clock pulses of the clock of the counting means 50,52 during the second selection means period after the electrical energy is supplied using the electrical energy stored in the storage means, and counting means 50,52 Reset state holding means (40) for releasing a reset state when the second predetermined time period ends such that the counting means starts counting, and the counting means triggers when the predetermined number of clock pulses in the clock pulse string is counted; Means 58 for generating a signal and means 17 for discharging electrical energy stored in the storage means to the ignition element in response to the trigger signal. Electronic delay circuit for igniting the ignition element. 17. The apparatus according to claim 16, further comprising means for over exciting the oscillating means (90), wherein said over filtered means (70) at said storage means (15) for a first time period after electrical energy has been supplied. Means for supplying a current to the oscillation means (90). 18. The comparator according to claim 17, wherein said reset state maintaining means (40) comprises a time constant circuit and a comparator (42), said time constant circuit comprising a capacitor (22) and a resistor (21), and said comparator (42). ) Is an electronic delay circuit for igniting an ignition element, characterized in that comparing the voltage across the capacitor with a predetermined reference voltage. 19. The electronic delay circuit according to claim 18, wherein the second selection time period of the reset state maintaining means (40) is equal to or shorter than 5 ms. 20. The ignition element as claimed in claim 19, further comprising a discharge means (17) connected in parallel with said storage means (15) in order to promote the discharge of said electrical energy stored in said storage means (15). Electronic delay circuit for igniting the lamp. 21. The electronic delay circuit as claimed in claim 20, wherein said counting means (50, 52) is a preset counter whose initial value is set by interrupting a preset wire. 22. The apparatus of claim 21, further comprising means for presetting an initial value of the preset counter, wherein the presetting means means for separating the presetting means from the storage means after the presetting of the initial value is completed. Electronic delay circuit for igniting an ignition element comprising a. 23. The electronic delay circuit as claimed in claim 22, further comprising a resistor connected between the wires carrying the electrical energy input to said storage means (15). The ignition element according to claim 23, wherein said oscillation means (90), counting means (50, 52), over-excitation means (70) and reset state maintaining means (40) are integrated in one IC chip. Electronic delay circuit for igniting the lamp.