JPH0719799A - Electronic detonator - Google Patents

Abstract

PURPOSE:To improve operability on the occasion of being fitted as a master die to explosives, by a method wherein a capacitor to be charged with electric energy supplied from a firing device is constructed of a chip capacitor. CONSTITUTION:When a capacitor 5 is supplied with electric energy from a firing device 22, it starts to be charged therewith, and a constant voltage circuit 6 receives a terminal voltage of the capacitor 5 as an input and outputs a prescribed constant voltage. When a thyristor 11 receives a signal as an input from a voltage comparator circuit 10, it closes the circuit and makes a resistor 12 for ignition electrified by the electric energy charged in the capacitor 5. Being electrified by the electric energy, the resistor 12 for ignition generates a heat and ignites a detonator. Herein the capacitor 5 is constructed by using a tantalum electrolytic capacitor of a resin mold chip of a capacitance 100muF and a rated voltage 6V. In this way, an electronic circuit part of an electronic detonator can be constructed to be slender and small in size.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an electronic detonator.

[0002]

2. Description of the Related Art For example, JP-A-57-142498 or JP-A-62-91799 describes an electronic delay detonator. FIG. 8 shows an example thereof. This electronic detonator uses the charging means 2 for charging the electric energy supplied from the blaster.
00, the load circuit outputs a signal after a preset operation by the electric energy charged in the charging means 200, and the switching circuit is closed by the signal output from the load circuit to charge the charging means 200. The generated electrical energy is supplied to the ignition resistance wire 201.

[0003]

However, in the above-mentioned electron detonator, the charging means 200 is not specified, and in general, an electrolytic capacitor is usually used.

Further, as an electrolytic capacitor used in an electron detonator, a cylindrical type having an electroleg has been considered as the mainstream in terms of performance such as capacitance and rated voltage.

Therefore, as shown in FIG. 9, the charging means 2
When 00 is the electrolytic capacitor described above, other electronic components (chip components) are mounted (bonded) on the printed circuit board 202 on which the cream solder printing is performed, and after passing through the soldering furnace (the above steps are automatically performed. There is a through hole for the electrolytic leg of the electrolytic capacitor on the substrate 202, and the electrolytic leg 200A must be passed through the through hole to be brazed to the substrate 202, which is a manual work. Was difficult to automate. Also,
Also in the production of an electron detonator, it was difficult to reduce the size in terms of shape if there was an electrolytic capacitor.

Therefore, an object of the present invention is to provide an electronic detonator that solves the above problems.

[0007]

According to the present invention, a means for charging electric energy supplied from a blasting machine and an electric energy charged in the charging means are operated, and a signal is output after a preset operation. In the electronic detonator, the charging circuit includes a load circuit for charging, and a switching circuit that is closed by a signal output from the load circuit and energizes the ignition resistance wire with the electric energy charged in the charging circuit. It is characterized by being composed of a capacitor.

Preferably, the charging means is a chip capacitor having a rated voltage of 4 V or more, and more preferably, the charging means has one or a plurality of chip capacitors connected in parallel according to the required electrostatic capacity. It is characterized by

[0009]

According to the present invention, the electronic circuit portion of the electron detonator can be made elongated and small in size, and it is not necessary to braze through the through hole, so that an advantageous component structure can be obtained in automating the manufacturing. .

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

<Embodiment 1> FIG. 1 shows an embodiment of an electronic detonator according to the present invention.

In the figure, a resistor 3 and a rectifier 4 are connected between the input terminals 1 and 2. Resistor 3 prevents stray currents, which often occur at the blast site, from charging capacitor 5 to a voltage that would ignite the detonator.

The rectifier 4 has a capacitor 5 connected to the input terminals 1 and 1.
It allows unidirectional charging regardless of the polarity of the input voltage supplied to 2.

A series circuit of a thyristor (switching element) 11 and an ignition resistor 12 is connected to both ends of the capacitor 5.

Further, the input terminal of the constant voltage circuit 6 is connected to both ends of the capacitor 5.

A series circuit of a resistor 8 and a capacitor 9 forming the time constant circuit 7 is connected in parallel to the output terminal of the constant voltage circuit 6.

Further, the voltage comparison circuit 10 is connected to the output terminal of the constant voltage circuit 6. Also, resistor 8 and capacitor 9
The terminal 21 to which is connected is connected to the voltage comparison circuit 10.

The output terminal of the voltage comparison circuit is the thyristor 11.
Is connected to the gate terminal of.

The capacitor 5 starts charging when it is supplied with electric energy from the blasting device 22, and the constant voltage circuit 6 receives the terminal voltage of the capacitor 5 and outputs a predetermined constant voltage.

In the present embodiment, the voltage comparison circuit 10 uses the output voltage of the constant voltage circuit 6 as the reference voltage. That is, the constant voltage circuit 6 is used as the reference voltage generating means.

The capacitor 9 is charged according to the time constant of the resistance value of the resistor 8 and the electrostatic capacity of the capacitor 9.

The voltage comparison circuit 10 compares the charging voltage of the capacitor 9 with the output voltage of the constant voltage circuit 6 and outputs a signal to the thyristor 11 when they become equal at a predetermined ratio.

When a signal is input from the voltage comparison circuit 10, the thyristor 11 closes the circuit and energizes the ignition resistor 12 with the electric energy charged in the capacitor 5.

The ignition resistor 12 generates heat when energized with electric energy and causes the detonator to ignite.

2A and 2B show the structure of the electron detonator of this embodiment.

The printed circuit board 19 has a resistor 3, a rectifier 4, a constant voltage circuit 6 and a thyristor 11 on one surface thereof.
The other side of 9 has capacitors 5-1 to 5-3, a resistor 8, a capacitor 9, and a voltage comparison circuit 10.

The above components are electrically wired according to the block diagram of FIG. Also, the capacitors 5-1 to 5-3
Are connected in parallel to the output terminals of the rectifier 4.

In this embodiment, the capacitors 5-1 to 5-1
5-3 was formed by using a resin-molded chip tantalum electrolytic capacitor having a capacitance of 100 μF and a rated voltage of 6V.
Its structure is shown in FIG. In this capacitor, one ends of an anode lead frame 301 and a cathode lead frame 302 are connected to both ends of a capacitor element 300, and the other ends of these frames are exposed on the surface of a resin mold 303. According to the different chip structure, for example, the printed circuit board 19 on which cream solder printing is performed
Capacitors 5-1 to 5-at the same time as other chip parts
3 is mounted and the soldering work is automatically completed by passing through the soldering furnace. Moreover, such a capacitor is smaller than the conventional cylindrical electrolytic capacitor, and therefore can contribute to downsizing of the electron detonator.

The input terminals 1 and 2 on the substrate 19 are plugs 16
Through, it is electrically coupled to the leg wire 23. On the other hand, the ignition resistor 12 is electrically coupled to the output terminal of the thyristor 11 and the (−) side terminal of the capacitor 5 through the plug 17. As the resistor 8, a resistor whose resistance value can be arbitrarily changed within a predetermined range is used, and the delay time can be set by the resistor 8.

Further, the ignition charge 1 is provided around the ignition resistor 12.
3 is arranged.

The embolus 16 and the embolus 17 are mechanically coupled to the substrate 19, and further are squeezed into the tubular body 18 to be mechanically coupled. From the bottom of the tube body 19, from the bottom, the charge 15 and the detonator 1
5 is pressed and placed.

<Embodiment 2> FIG. 4 is a block diagram showing an embodiment according to the present invention.

In the figure, input terminals 31 and 32 are provided.
Is connected to an electric blaster via lead 151. A resistor 33 and a rectifier 34 are connected between the input terminals 31 and 32. Capacitor 35 and resistor 36
Are connected in parallel between the output terminals of the rectifier 34. The resistor 33 is a capacitor 3 up to a voltage at which the stray current that often occurs at the blasting site ignites the detonator.
Prevent charging of 5. Further, the resistor 33 functions as a voltage divider that applies substantially equal voltage to each rectifier 34 when a plurality of detonators are connected in series in the multistage blasting system. Rectifier 34 allows capacitor 35 to be charged in one direction regardless of the polarity of the input voltage supplied to terminals 31 and 32. in this case,
The capacitor 35 is charged by the electric energy supplied from the electric blaster 1 to a maximum voltage of 35 V in 5 to 10 ms.

A series circuit of a thyristor (switching element) 37 and an ignition resistor 38 is connected to both ends of the capacitor. Further, the input terminal of the constant voltage circuit 39 is connected to both ends of the capacitor 35. Capacitor 50
A series circuit of the resistor 51 and the capacitor 52 is connected in parallel between the output terminals of the constant voltage circuit 39. Resistance 3
1 and the capacitor 32, the counter reset time circuit 33
Are configured. Further, the digital timer 50 is connected to the output terminal of the constant voltage circuit 39.

The digital timer 50 includes a reset circuit 6
0, a main counter 70 for counting the delay time for igniting the detonator, a preset circuit 80 for presetting an initial value of the main counter, an over-excitation circuit for over-exciting the oscillator 110 so that the oscillator 110 enters a steady state in an extremely short time. It is composed of 90.

The reset circuit 60 comprises a comparator 62 and a voltage divider composed of resistors 64 and 66. The inverting input terminal of the comparator 62 has a resistor 41 and a capacitor 42.
Of the comparator 62, and the non-inverting input terminal of the comparator 62 is connected to the connection point of the resistors 64 and 66.
Therefore, the output of the comparator 62 changes from the high level to the low level after a predetermined time T1 defined by the time constant of the resistor 41 and the capacitor 42. The predetermined time T1 is defined as, for example, 5 ms, which corresponds to the counter reset time of the present invention.

The main counter 70 is a 13-bit preset type counter to which the pulse train is supplied from the frequency divider 72. The frequency divider 72 is a 12-bit frequency divider. That is, the output frequency of the frequency divider 72 is 1/4096 of the frequency of the clock pulse train Se supplied from the oscillator 110.

The main counter 70 is connected to a preset circuit 80 which presets the initial value of the main counter 70. The preset circuit 80 is driven by the flip-flop 76. This flip-flop 76 outputs the signal S
It is reset at the rising edge of R. On the other hand, the main counter 70
The frequency divider 72 is reset at the falling edge of the signal SR.

FIG. 5A shows a plurality of switching circuits 82.
1 shows a preset circuit 80. Each switching circuit 82 is connected in series via a resistor 87 to p-
It is composed of a channel FET 84 and an n-channel FET 86. The gates of the two FETs are connected to the Q output of the flip-flop 76. When the flip-flop 76 is in the set state, that is, when the gate voltage is higher than the threshold voltage, the p-channel FET 84 is turned off and the n-channel FET is turned on. Therefore, the output level of each switching circuit 82 is low, and the preset value of the main counter 70 does not change. vice versa,
When the flip-flop 56 is in the reset state, that is,
If the gate voltage is below the threshold voltage, p-channel FET 84 is conductive and n-channel FET 86 is cut off. In this case, each switching circuit 82
Output level of the time set lines 88-1, 88-
2 ,. ． ． It is determined by the state of 88-m. If the time set line 88-j is grounded, the switching circuit 8
2 output level is low, but time set line 88
High when j is open.

In FIG. 4, the output of the main counter 70 is supplied to the flip-flop 78, which sets the flip-flop 78 which was previously reset at the rising edge of the signal SR. When the flip-flop 78 is set, the thyristor 37 is triggered and turned on. That is, all the electrical energy remaining in the capacitor 35 after being consumed by the delay circuit is supplied to the ignition resistor 38 and the detonator explodes.

The overexcitation circuit 90 includes an auxiliary counter 92, flip-flops 94-1, 94-2 ,. ． ． 94-n,
The clocked inverters 96-1, 96-2 ,. ． ． 96
-N and an inverter 98. The counter 92 outputs signals R1, R2. ． ． Rn is output, and this is flip-flops 94-1 and 94-
2 ,. ． ． It is supplied to each reset terminal of 94-n. The flip-flops 94-1, 94-2 ,. ． ． 94
-N is simultaneously set at the rising edge of the signal SR, and the signal R
1, R2 ,. ． ． It is sequentially reset by Rn. The output terminal of the flip-flop 94-i (i = 1, 2, ..., N) is connected to the control terminal of the clocked inverter 96-i. The overexcitation circuit itself is disclosed in
Known in the field of electronic circuits, as disclosed in FIG. 9 of 200009.

FIG. 5B shows a clocked inverter 96-
It is a circuit diagram of i. This clocked inverter 96-i
Control terminals 103 and 104 of the flip-flop 9
It is connected to the output terminal of 4-i. Input terminal 101 and output terminal 102 of the clocked inverter 96-i
Are connected to the oscillator 110. When a high level signal is applied to the control terminal 103 and a low level signal is applied to the control terminal 104, the clocked inverter operates as an inverter. On the other hand, when a low level signal is applied to the control terminal 103 and a high level signal is applied to the control terminal 104, the clocked inverter is electrically disconnected from the oscillator 110.

The oscillator 110 comprises a crystal oscillator 112, a feedback resistor 114 connected in parallel with the crystal oscillator 112, and capacitors 116 and 118 connected between the crystal oscillator 112 and the ground. The crystal oscillator preferably has a frequency of 1 MHz to 16 MHz.
It is in the MHz range. If the frequency is too low, the rise time of oscillation becomes long. As a result, the counter reset time T1 increases, and the accuracy of the delay time is adversely affected. If the frequency is too high, it will increase power consumption. As a result, the capacitor 35 cannot supply enough electrical energy to explode the detonator.

Next, the operation of the delay circuit of FIG. 4 will be described with reference to FIG.

FIG. 6 shows the waveform of each part of the delay circuit.

At time t0, the voltage Sa is applied to the input terminals 31 and 32 from the electric blaster 1. The electric energy given by the voltage Sa is stored in the capacitor 35, and the voltage Sb of the capacitor 35 rapidly increases. The constant voltage circuit 39 immediately after the application of the voltage Sa (several microseconds)
Of the constant voltage Sc (for example, 3.
3V) is output.

The constant voltage Sc is applied to the capacitor 42 via the resistor 41, and the voltage Sd of the capacitor 42 gradually increases. When the voltage Sd exceeds the voltage determined by the voltage divider composed of the resistors 64 and 66 at time t2, the comparator 62
Output level changes from high to low, and this change makes the signal SR fall. That is, when the time interval T1 (about 5 ms in this embodiment) elapses after the time t1,
The falling edge of the signal SR is generated. Signal SR is at time t
At its rising edge in 1, flip-flop 94-1
~ 94-n are set and flip-flops 76 and 7
8 is reset. On the other hand, the signal SR resets the main counter 70, the frequency divider 72, and the counter 92 at the falling edge thereof at the time t2.

During the time interval T1, the crystal oscillator 112 is
Is overexcited by the clocked inverters 96-1 to 96-n and the inverter 98 and enters a steady state. That is, the frequency of the pulse train output from the crystal oscillator 112 is stabilized during the time interval T1.

At time t2, the frequency divider 72 starts to operate,
A pulse train Sf consisting of pulses with an interval of 1 ms is output. At the same time, the counter 92 starts counting clock pulses supplied from the crystal oscillator 110 and generates signals R1 to Rn at intervals of 1 μs. Signal R1 is at time t2
The flip-flop 76 is set and the flip-flop 94-1 is reset at a time t3 1 μs after. Therefore, the signal Sg applied to the preset circuit 80 rises at time t3, and the preset circuit 80 is turned on by the constant voltage circuit 3.
Separate from 9. This reduces the power consumption by the delay circuit.

After the time t3, the flip-flop 94-
1 to 94-n are signals Sh (= R1, R2, ... Rn)
By this, the data are sequentially reset at every T2 interval (1 μs). Therefore, the clocked inverters 96-1 to 96-96
-N is sequentially cut off from the oscillator 90. That is, the overexcitation of the oscillator 110 is gradually released by the signal Sh. As a result, the current Si supplied to the crystal oscillator 110 is from 20 mA supplied from the clocked inverter 96 and the inverter 98 at the start of overexcitation,
Gradual to 0.2 mA, which is supplied by the inverter 98 during steady excitation.

The crystal oscillator 112 consumes a considerable amount of power in the initial stage of oscillation and automatically reduces its power consumption as the oscillation approaches a steady state. Therefore, over-excitation of the crystal oscillator by the clocked inverter driven by the constant voltage does not cause thermal damage to the oscillator and leads oscillation to a steady state in an extremely short time.

By utilizing this feature of the crystal oscillator, the clocked inverter 96 and the inverter 98 can be utilized.
Can be replaced by an inverter that can supply sufficient current to induce over-excitation of the crystal oscillator. In this case, the clocked inverter 76 and the flip-flop 94 can be omitted.

When the current value of the main counter 70 reaches the preset value, the main counter 70 sets the flip-flop 78. This produces a trigger signal Sj for the thyristor 37 and a current Sk is supplied from the capacitor 35 to the ignition resistor 38. In this way, the detonator explodes.

When the detonation time of the electronic delay detonator manufactured according to this example was measured, the results shown in the table below were obtained,
It was confirmed that detonation was possible within the error range of ± 1 ms with respect to the set detonation time interval.

[0055]

[Table 1]

7 (a) and 7 (b) show the structure of the electron detonator of this embodiment.

On one surface of the substrate 152, the resistor 33, the rectifier 34, the constant voltage circuit 39, the capacitors 116 and 118,
The feedback resistor 114, the capacitor 40, the crystal oscillator 112, the capacitor 42, the resistor 41, the digital timer 50, and the thyristor 37 are provided, and the capacitors 35-1 to 35-7 and the time set line are provided on the other surface of the substrate 152. 88 is printed on the substrate 152.

The above components are electrically wired according to the block diagram of FIG. In addition, capacitors 35-1 to 35
Each -7 is connected in parallel to the output terminal of the rectifier 34.

In this embodiment, the capacitors 5-1 to 5-3 are formed by using the resin-molded chip tantalum electrolytic capacitors having an electrostatic capacity of 100 μF and a rated voltage of 6 V, as in the first embodiment. Therefore, as in the first embodiment, the soldering work is automated and the size is small, which can contribute to downsizing of the electron detonator.

The input terminals 31 and 32 on the substrate 152 are electrically coupled to the leg wire 151 through the plug 131.
On the other hand, the ignition resistor 38 is electrically coupled to the output terminal of the thyristor 37 and the terminal of the capacitor 35 (−) side through the plug 132.

Further, the ignition charge 1 is provided around the ignition resistor 38.
41 is arranged.

The embolus 131 and the embolus 132 are provided on the substrate 15
2 is mechanically coupled to the pipe body 150, and the pipe body 150 is further squeezed and mechanically coupled.

From the bottom of the tubular body 150, the additive 143 and the detonator 142 are pressed and arranged.

[0064]

According to the present invention, since the capacitor for charging the electric energy supplied from the blasting device is composed of the chip capacitor, it can be constructed as a long and small electronic detonator and can be mounted on the explosive as the parent die. The property is improved.

Further, in the case of manufacturing, the number of parts to be brazed through the through hole is reduced, so that the working cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an electronic detonator according to the present invention.

FIG. 2 is a structural diagram showing a first embodiment of an electron detonator according to the present invention.

FIG. 3 is a structural diagram of a chip capacitor in the same example.

FIG. 4 is a block diagram showing a second embodiment of the electronic detonator according to the present invention.

5A is a circuit diagram showing the preset circuit of FIG. 4, and FIG. 5B is a circuit diagram showing the clocked inverter of FIG.

6 is a diagram showing a waveform of each part of FIG.

FIG. 7 is a structural diagram showing a second embodiment of the electron detonator according to the present invention.

FIG. 8 is a structural diagram of a conventional electron detonator.

FIG. 9 is a side view of a printed circuit board portion of the electronic detonator.

[Explanation of symbols]

 1, 2 Input terminals 3 Resistance 4 Rectifier 5 Capacitor 6 Constant voltage circuit 7 Time constant circuit 8 Resistance 9 Capacitor 10 Voltage comparison circuit 11 Switching circuit 12 Ignition resistor 13 Ignition charge 14 Explosive charge 15 Addition charge 16 Embolization 17 Embolization 18 Tube Body 19 Substrate 21 Terminal 22 Blaster 23 Leg wire 31, 32 Input terminal 33 Resistor 34 Rectifier 35 Capacitor 35-1 to 35-7 Capacitor 36 Resistor 37 Thyristor 38 Ignition resistor 39 Constant voltage circuit 40 Capacitor 41 Resistor 42 Capacitor 43 Reset Time circuit 50 Digital timer 60 Reset circuit 62 Analog comparator 64,66 Resistance 70 Main counter 72 Frequency divider 76,78 Flip-flop 80 Preset circuit 82 Switching circuit 84 p-channel FET 86 n-channel ET 87 resistance 88 hour set line 88-1 to 88-m time set line 90 overexcitation circuit 92 auxiliary counter 94-1 to 94-n flip-flop 101 clocked inverter input terminal 102 clocked inverter output terminal 103, 104 Control terminal 110 Oscillator 112 Crystal oscillator 114 Feedback resistance 116, 118 Capacitor 131 Embroidery 132 Emboli 141 Ignition charge 142 Explosive 143 Addition charge 150 Tubing 151 Leg wire

Claims (5)

[Claims] 1. A means for charging electric energy supplied from a blaster, a load circuit which operates by the electric energy charged by the charging means and outputs a signal after a preset operation, and the load circuit. An electronic detonator including a switching circuit that closes by a signal output from the charging means and energizes the ignition resistance wire with the electric energy charged in the charging means, wherein the charging means includes a chip capacitor. Electronic detonator. 2. The electronic detonator according to claim 1, wherein the charging means comprises a chip capacitor having a rating of 4 V or higher. 3. The electron detonator according to claim 1, wherein the charging means comprises a plurality of chip capacitors. 4. The electronic detonator according to claim 1, wherein the load circuit comprises a delay circuit including an oscillation circuit and a means for counting the output of the oscillation means. 5. The load circuit according to claim 1, wherein the load circuit comprises a time constant means composed of a resistor and a capacitor, a reference voltage generating means, and a means for comparing the charging voltage of the capacitor of the time constant means with the reference voltage. An electronic detonator characterized by comprising a delay circuit provided.