KR960012598B1 - Digital color-space converting circuit - Google Patents

Abstract

The circuit comprises a decoder(10) for generating an enable signal, a luminance signal calculating unit(11) for calculating the signal and X,Y,Z component of input value(KA), the first color signal calculating unit(16,32,37) for calculating the signal(U/I) and X,Y,Z component of input value(KB), the second color signal calculating unit(KC) (22,37,52), the first adder(60) for generating R signal, the second adder(70) for generating G signal, and the third adder(80) for generating B signal.

Description

Digital Color Space Conversion Circuit

1 is a block diagram showing a conventional digital color space conversion circuit.

2 is a block diagram showing a digital color space conversion circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

10 decoder 11 luminance signal multiplier

16,32,37: U signal multiplier 22,37,52: V signal multiplier

60,70,80: adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital color space conversion circuit, and more particularly, to a digital color space conversion circuit that maintains a matrix method and reduces the size of a device.

In general, digital color space converters have a matrix structure. The digital color space converter has a function of receiving the luminance signal Y and the color signals U / I, V / Q as inputs and converting them into color signals R, G, and B.

In other words, if the input data is referred to as the luminance signal (Y) color signal (U, V), and the coefficients required for conversion are KAX, KAY, KAZ, KBX, KBY, KBZ, KCX, KCY, KCZ, the output R, G, B Can be expressed as:

R = Y ＊ KAX + U ＊ KBX + V ＊ KCX (1)

G = Y ＊ KAY + U ＊ KBY + V ＊ KCY (2)

B = Y ＊ KAZ + U ＊ KBZ + V ＊ KCZ (3)

1 is a block diagram showing a conventional digital color space conversion circuit.

1 is a circuit of the equations (1), (2), and (3). The decoder 10 outputs an enable signal to hold or load data, and the enable of the decoder 10. The first luminance signal multiplier 11 for transmitting the luminance signal Y and the coefficient KAX of the X component in accordance with the signal, and the luminance signal Y and the Y component in accordance with the enable signal of the decoder 10. A second luminance signal multiplier 16 that multiplies the coefficient KAY, and a third luminance signal multiplier that multiplies the luminance signal Y and the coefficient KAZ of the Z component according to the enable signal of the decoder 10. The first U signal multiplier 26 multiplying the U signal by the coefficient KAX of the X component according to the enable signal of the decoder 10, and the enable signal of the decoder 10. The second U signal multiplier 31 multiplying the U signal and the coefficient KAY of the Y component, and the third U multiplying the coefficient KAZ of the Z component of the U signal according to the enable signal of the decoder 10. God A multiplier 36, a first V signal multiplier 41 for multiplying the V signal and the coefficient KAX of the X component according to the enable signal of the decoder 10, and the enable signal of the decoder 10. The second V signal multiplier 46 multiplies the V signal and the coefficient KAY of the Y component according to the second signal and the coefficient KAZ of the Z component and the Z component according to the enable signal of the decoder 10. The output of the 3 V signal multiplier 51, the first adder 60 for adding the outputs of the first to third luminance signal multipliers 11, 16, 21, and the first adder 60 is temporarily suspended. Temporarily latches the output of the second adder 70 and the second adder 70 that adds the register 65 to latch, the outputs of the first to third U signal multipliers 26, 31, and 36. A register 75, a third adder 80 for adding the outputs of the first to third V signal multipliers 41, 46, and 51, and a register for temporarily latching the output of the third adder 80 ( 85).

In addition, the first luminance signal multiplier 11 is a register 12 for receiving the enable signal from the decoder 10 to the enable end and the coefficient KA to the input terminal and outputs the coefficient value of the X component, A register 13 for receiving the luminance signal Y at an input terminal, an adder 14 for multiplying the output of the registers 12 and 13 when the enable terminal of the register 12 is enabled, and The multiplier 14 for operation and a register 15 for temporarily latching the output of the multiplier 14 for high speed operation.

Meanwhile, the second and third luminance signal multipliers 16 and 21 and the first to third U signal multipliers 26, 31, and 36, and the first to third V signal multipliers 41, 46, and 51 ) Is the same as the configuration of the first luminance signal calculator 11 except that the input signal is different.

In FIG. 1 configured in this manner, input data Y is input into registers 13, 28, and 43, U is input into registers 18, 33, and 48, and V is input into registers 23, 38, and 53, respectively. do.

The coefficient KA is input to the registers 12, 27 and 42, the coefficient KB is input to the registers 17, 32 and 47, and the coefficient KC is input to the registers 22, 37 and 52. In this case, the registers 12, 17, 22, 27, 32, 37, 42, 47, and 52 are enabled according to the enable value output from the decoder 10 to output data of a corresponding coefficient to the multiplier.

That is, the enable value is output from the decoder 10. When the output value of the decoder 10 is 1, the registers 12, 17, 22 are enabled, and when 10, the registers 27, 32, 37 are When enabled, at 11, registers 42, 47, and 52 are enabled to output the input coefficients and otherwise remain in the holding state.

In addition, when the output value of the decoder 10 is 0, all of the registers 12, 17, 22, 27, 32, 37, 42, 47, and 52 are in a holding state.

Therefore, the input coefficients KA, KB, and KC, each of which has three components, correspond to KAX, KAY, and K registers in the registers 12, 17, 22, 27, 32, 37, 42, 47, and 52 according to the output of the decoder 10. KAZ,… It will load KCX, KCY and KCZ.

Then, the loaded coefficient and the input data are multiplied by the multiplier according to the output of the decoder 10. That is, since the output of the decoder 10 is 1, the register 12 of the first luminance signal multiplier 11 and the register 17 of the first U signal multiplier 16 and the first V signal multiplier 21 When the register 22 is enabled, the multiplier 14 of the first luminance signal multiplier 11 multiplies the coefficient KAX output from the register 12 and the luminance signal Y output from the register 13. After that (KAX * Y), the pipe lining register 15 is temporarily latched for high speed operation.

The multiplier 19 of the first U signal multiplier 16 multiplies the coefficient KBX output from the register 17 by the color signal U output from the register 18 (KBX * U), Temporarily latches in pipe lining register 20 for high speed operation.

The multiplier 24 of the first V signal multiplier 21 multiplies the coefficient KCX output from the register 22 and the color signal V output from the register 23 (KCX * V). It is also temporarily latched in the pipe lining register 25 for high speed operation.

Then, the adder 60 outputs the output of the register 15 of the first luminance signal multiplier 11 (KAX * Y) and the output of the register 20 of the first U signal multiplier 16 (KBX *). U) and the output (KCX * V) of the register 25 of the first V signal multiplier 21 are added (Y * KAX + V * KBX + V * KCX).

The output of the adder 60 is output as an R signal through a register 65 for pipe lining.

On the other hand, when 10 is output from the decoder 10, the adder 70 outputs the output of the second luminance signal multiplier 26 (KAY * Y) and the output of the second U signal multiplier 31 (KBY * U) and The output (KCY * V) of the second V signal multiplier 37 is added and then output as a G signal through the register 75 for pipe lining.

In addition, when 11 is output from the decoder 10, the adder 80 outputs the output of the third luminance signal multiplier 41 (KAZ * Y) and the output of the third U signal multiplier 46 (KBZ * U) and The output KCZ * V of the third V signal multiplier 51 is added and then output as a B signal through a register 85 for pipe lining.

As described above, the above operation is to multiply the input data Y, U, and V by constant coefficients to convert them to R, G, and B. The conversion equations and conversion coefficients are expressed by the following equations (1), (2) and Same as (3).

R = KAX ＊ Y + KBX ＊ U + KCX ＊ V (1)

G = KAY ＊ Y + KBY ＊ U + KCY ＊ V (2)

B = KAZ ＊ Y + KBZ ＊ U + KCZ ＊ V (3)

In this case, I and Q may be used instead of the color signals U and V. FIG.

Table 1 below shows a loading / holding state diagram of coefficients according to the values of SEL [1: 0] input to the decoder 10.

TABLE 1

In addition, the color space conversion coefficients used to convert the input signals Y, U / I, V / Q into R, G, and B are shown in Table 2 below.

TABLE 2

Here, numbers starting with 2 and 3 represent two's complement and all numbers represent 10-bit hexadecimal numbers.

As described above, the digital color space converter is widely used for equipment that needs to convert color components such as YUV, YIQ, RGB, etc., color matching equipment between systems such as cameras, image acquisition / processing and storage devices, cameras and monitors, and the like. have.

In addition, such equipment is required to be as small as possible and light in size to facilitate user convenience.

Accordingly, an object of the present invention is to use a matrix structure by reducing the number of multipliers and registers by using the input coefficients KAX, KAY, and KAZ are always input to the same value, but to reduce the size of the device to reduce the size of the product digital To provide a color space conversion circuit.

A feature of the digital color space conversion circuit according to the present invention for achieving the above object is a decoder for outputting an enable signal for holding or loading data, and a luminance signal Y in accordance with the enable signal of the decoder. ) And a luminance signal multiplier for multiplying the K, Y, and Z components of the input coefficient KA, and the X, Y of the color signal U / I and the input coefficient KB according to the enable signal of the decoder. And a first color signal multiplier for multiplying the Z components, and a multiplier for multiplying the X, Y, and Z components of the color signal V / Q and the input coefficient KC according to the enable signal of the decoder. A two-color signal multiplier, a first adder for adding the multiplication result of the Y, U / I, V / Q and the input coefficient values KAX, KBX, KCX and outputting it as an R signal, and the Y, U / I, V A second adder for adding a multiplication result of / Q with the input coefficient values KAY, KBY, KCY and outputting the result as a G signal, and the Y, U / I, V / Q and input coefficient values KAZ, KBZ, K In a digital color space conversion circuit comprising a third adder for adding a multiplication result of CZ and outputting the result as a B signal, the luminance signal multiplier includes a multiplier and a pipe for multiplying the input coefficient KA and the luminance signal Y. It is composed of a predetermined register for lining and outputs a multiplication result of the X, Y, Z components of the input coefficient KA and the luminance signal Y in accordance with the enable value provided from the decoder.

Hereinafter, a preferred embodiment of a digital color space conversion circuit according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a digital color space conversion circuit according to the present invention, in which first to third luminance signal multipliers receiving an input coefficient KA and a luminance signal Y are reduced to one luminance signal multiplier 11. Except for the above, the same as in the conventional first embodiment described above.

That is, as shown in [Table 2], the values of the X, Y, and Z components of KA are the same among the conversion coefficients from YIQ or YUV to RGB. Accordingly, the same operation is performed without using two multipliers constituting the second and third luminance signal multipliers of FIG. 1 and a series of registers for pipe lining.

Accordingly, in FIG. 2, when the output of the decoder 10 is 1, the register 12 of the luminance signal multiplier 11 and the register 17 of the first U signal multiplier 16 and the first V signal multiplier ( The register 22 of 21 is enabled, and the multiplier 14 of the luminance signal multiplier 11 outputs the coefficient KAX output from the register 12 and the luminance signal Y output from the register 13. After multiplying by (KAX * Y), the pipe lining register 15 is temporarily latched for high speed operation.

The multiplier 19 of the first U signal multiplier 16 multiplies the coefficient KBX output from the register 17 by the color signal U output from the register 18 (KBX * U). It is temporarily latched in the pipe lining register 20 for high speed operation.

The multiplier 24 of the first V signal multiplier 21 multiplies the coefficient KCX output from the register 22 and the color signal V output from the register 23 (KCX * V). Temporarily latches in pipe lining register 25 for high speed operation.

Then, the adder 60 outputs the output of the register 15 of the first luminance signal multiplier 11 (KAX * Y) and the output of the register 20 of the first U signal multiplier 16 (KBX * U). ) And the output (KCX * Y) of the register 25 of the first V signal multiplier 21 (Y * KAX + U * KBX + V * KCX).

The output of the adder 60 is output as an R signal through a register 65 for pipe lining.

In this case, since the coefficients KAX, KAY, and KAZ output from the luminance signal multiplier 11 are all the same value, when the Y signal is converted into an R signal, that is, when the output of the decoder 10 is 01, the luminance signal multiplier The register 12 of (11) outputs the coefficient KAX, and when the U or I signal is converted to the G signal, that is, when the output of the decoder 10 is 10, the register 12 outputs the coefficient KAY, When the V or Q signal is converted to the B signal, that is, when the output of the decoder 10 is 11, the register 12 outputs the coefficient KAZ.

Then, the adder 70 outputting 10 from the decoder 10 outputs the output of the luminance signal multiplier 11 (KAY * Y) and the output of the second U signal multiplier 31 (KBY * U). After the output KCY * V of the 2V signal multiplier 37 is added, it is output as a G signal through the register 75 for pipe lining.

In addition, when 11 is output from the decoder 10, the adder 80 outputs the output of the luminance signal multiplier 11 (KAZ * Y) and the output of the third U signal multiplier 46 (KBZ * U) and the first. After the output KCZ * V of the 3V signal multiplier 51 is added, it is output as a B signal through the register 85 for pipe lining.

Therefore, the conversion equation and conversion coefficient for multiplying the input data Y, U / I, V / Q by a constant coefficient and converting them into R, G, and B are as follows.

R = KAX ＊ Y + KBX ＊ U + KCX ＊ V (1)

G = KAY ＊ Y + KBY ＊ U + KCY ＊ V (2)

B = KAZ ＊ Y + KBZ ＊ U + KCZ ＊ V (3)

As described above, according to the digital color space conversion circuit according to the present invention, the multipliers and pipes for multiplying the coefficients KAX and Y are equal because the values of the X, Y, and Z components of KA are the same among the conversion coefficients from YIQ or YUV to RGB. By performing the same operation as before using only a series of registers for lining, it is necessary to reduce the size of the device to convert color components such as YUV, YIQ, RGB, ie, color component converter, broadcasting equipment, system, camera and The economical efficiency is achieved by miniaturizing the color matching device between monitors.

Claims (1)

A decoder that outputs an enable signal for holding or loading data, and a luminance signal multiplier for multiplying the luminance signal Y and the X, Y, and Z components of the input coefficient KA according to the enable signal of the decoder A first color signal multiplier for multiplying the X, Y, and Z components of the color signal (U / I) and the input coefficient (KB) according to the enable signal of the decoder, and the enable signal of the decoder A second color signal multiplier for multiplying the X, Y, and Z components of the color signal V / Q and the input coefficient KC according to And a first adder for adding the multiplication result of KBX, KCX and outputting it as an R signal, and adding the multiplication result of the Y, U / I, V / Q and input coefficient values KAY, KBY, KCY and outputting it as a G signal. A digital color space conversion circuit comprising a second adder and a third adder for adding the result of multiplication of the Y, U / I, V / Q and the input coefficient values KAZ, KBZ, KCZ and outputting the result as a B signal. The luminance signal multiplier comprises one multiplier for multiplying the input coefficient KA and the luminance signal Y and a predetermined register for pipelining, and according to the enable value provided from the decoder, Outputting a multiplication result of the X, Y, Z component of KA) and the luminance signal (Y).