KR960011957B1 - The selection method of spare word-line of semiconductor memory device - Google Patents

Abstract

The method is for preventing the racing problem by selecting the normal word line and the spare word line simultaneously. The method comprises the steps of: generating a word line turn-on power according to a word line enable signal and a repair signal; and selecting the spare word line by supplying the word line turn-on power to the spare word line according to a X-decoder precharge signal and a block selecting address signal.

Description

Spare word line selection method of semiconductor memory device

1 is a circuit diagram for explaining a spare word line selection method of a conventional semiconductor memory device.

2 is a circuit diagram for explaining a spare word line selection method of a semiconductor memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

1 and 3: power supply for spare word line selection 2 and 4: spare word line selection

The present invention relates to a method of selecting a spare word line of a semiconductor memory device, and more particularly, a method of selecting a spare word line of a semiconductor memory device in which a normal word line and a spare word line are selected at the same time so that a occurrence of a racing problem can be prevented. It is about.

In general, a memory device such as DRAM (DRAM) is composed of a memory cell array and a peripheral circuit, and the memory cell array is divided between a word line and a bit line. Memory cells are connected and configured in a matrix manner. In addition, the memory cell array is provided with a spare memory cell (or a redundancy memory cell) to prevent a decrease in yield due to a failure of a normal memory cell, and a repair is performed when a failed normal memory cell is selected. The spare memory cell is selected using the () signal. At this time, a high potential word line turn-on power supply Vpp is supplied to the word line of the selected spare memory cell, and no power is supplied to the word line of the normal memory cell. However, when the failed normal memory cell and the spare memory cell are selected, the word lines of the two memory cells are not simultaneously selected due to a time delay (for example, when the spare memory cell is selected before the failed normal memory cell). That is, a racing problem occurs, whereby the operating characteristics of the device are deteriorated.

Such a racing problem is caused by a time delay caused by different types of signals used to select a word line of a normal memory cell and a signal used to select a word line of a spare memory cell. A method of selecting a spare word line of a memory device will be described with reference to FIG. 1.

FIG. 1 is a circuit diagram illustrating a spare word line selection method of a conventional semiconductor memory device, and includes a high potential pump 5 and outputs a word line turn-on power supply Vpp according to a block selection signal and a repair signal. A line select power supply unit 1 and a spare word line select unit 2 for supplying the word line turn-on power supply Vpp to a spare word line according to the block select signal will be described.

When the block selection signal and the repair signal are input to the NAND gate G1 of the spare word line selection power supply 1 in a high potential state, the output of the NAND gate G1 is in a low potential state. The output of the NAND gate G1 is inverted to a high potential state through the inversion gate G2, and the transistor Q6 of the high potential pump 5 is turned on by the output of the inversion gate G2. )do. Therefore, the potential of the node N1 becomes a low potential state, whereby the transistor 1 is turned on. Therefore, the high potential Vpp, that is, the word line turn-on power supply Vpp is applied to the node N2 by the operation of the transistor Q1, and the word line turn-on power supply Vpp is the spare word line selector ( 2) is output. In addition, the block selection signal is sequentially passed through the inversion gates G3 and G4 of the spare word line selector 2, and then the potential is increased by the threshold voltage of the transistor by the Bostrap transistor Q12. The transistor Q10 is turned on by the elevated high potential, and the word line turn-on power supply Vpp is supplied to the spare word line by the operation of the transistor Q10. That is, the spare word line is driven by the block selection signal and a signal for determining whether to repair the repair signal.

Through the above process, the word line of the failed normal memory cell while the word line of the spare memory cell is selected is also selected. The word line of the normal memory cell is selected by a word line enable signal and a word line select address signal. However, as described above, since the types of signals used when selecting the spare word line and the normal word line are different from each other, a time delay occurs, thereby causing a racing problem and deteriorating operation characteristics of the device. Therefore, in order to prevent this, the speed should be adjusted so that the selection time of the normal word line and the spare word line is the same. In addition, normal word lines are precharged by precharge immediately after the address is disabled, but spare word lines are not the same as normal X-decoder. There is a racing problem between the lines.

Accordingly, the present invention uses a word line enable signal and a repair signal for selecting a word line of a normal memory cell as inputs of a spare word line selection power supply unit, and a normal X-decoder precharge signal and a block select address signal as a spare word. It is an object of the present invention to provide a method of selecting a spare word line of a semiconductor memory device which can solve the above-described disadvantages by using the input of the line selector.

According to an aspect of the present invention, there is provided a power supply for turning on a word line according to a word line enable signal and a repair signal, and from the step, the word according to an X-decoder precharge signal and a block selection address signal. The line turn-on power supply is supplied to the spare word line, so that the spare word line is selected.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a circuit diagram for explaining a spare word line selection method of a semiconductor memory device according to the present invention.

The word line enable signal is input to one terminal of the NAND gate G7 of the spare word line selecting power supply unit 3 at a high potential state, and a power supply voltage Vcc is input to the other terminal of the NAND gate G7. When the output of the NAND gate G7 is a low potential state. The low potential of the NAND gate G7 is inverted to a high potential through the inversion gate G8 and then input to one terminal of the NAND gate G1. At this time, a repair signal is input to the other terminal of the NAND gate G1 in a high potential state. Therefore, the output of the NAND gate G1 becomes a low potential state, and the output of the NAND gate G1 is inverted to a high potential via the inversion gate G2. The transistor Q6 of the high potential pump 5 is turned on by the output of the inverted gate G2, whereby the node N1 is turned to the low potential state, thereby turning on the transistor Q1. Therefore, the high potential Vpp, that is, the word line turn-on power supply Vpp is applied to the node N2 by the operation of the transistor Q1, and the word line turn-on power supply Vpp is the spare word line selector 4. Will be printed). In addition, when the X-decoder precharge signal and / or the block selection address (A × BA and A × 89) signals are input to the spare word line selector 4 in a high potential state, the transistor Q14 is turned off. Transistors Q15 and Q16 are turned on so that node N3 is at the low potential state. After the inversion gate G5 is inverted to a high potential state, the potential of the node N3 is increased by the threshold voltage of the transistor by the strap transistor Q12. The transistor Q10 is turned on by the raised high potential, whereby the word line turn-on power supply Vpp is supplied to the spare word line.

As described above, according to the present invention, a word line enable signal and a repair signal for selecting a word line of a normal memory cell are used as inputs for a spare word line selection power supply and a normal X-decoder precharge signal and a block selection address. By using the signal as the input of the spare word line selector, the normal word line and the spare word line are simultaneously selected to prevent the occurrence of a racing problem. In addition, no racing problem occurs during the precharge operation. Therefore, the deterioration of the operating characteristics of the device due to the racing problem is prevented has an excellent effect that can improve the reliability of the device.

Claims (1)

A method of selecting a spare word line of a semiconductor memory device, the method comprising: generating a power supply for turning on a word line according to a word line enable signal and a repair signal; and from the step, according to the X-decoder precharge signal and a block selection address signal. A word word turn-on power supply is supplied to a spare word line so that the spare word line is selected.