KR960010481B1 - Video signal noise-eliminating integrated circuit apparatus using correlation between samples - Google Patents

Abstract

a delaying and adding means (1) for generating a number of added signals corresponding to the sum of two out of a number of pixels separated by the period of a color carrier; a correlation detecting means (3) for generating a correlation coefficient indicating the correlation between the pixels; a filter coefficient generating means (4) for generating a number of filter coefficient selection signals in order to select a combination of a number of added signals in response to the correlation coefficients; and a filtering means (3) for selecting a combination of the added signals based on the filter coefficient selection signals from the filter coefficient generating means, and outputting a digital image signal having the pixels without of a noise.

Description

Noise Reduction Device for Digital Video Signal Using Correlation Detection between Pixels

1 is a block diagram showing an apparatus for removing noise by detecting correlation between frames using a conventional frame memory,

2 is a block diagram showing an apparatus for removing noise of an image signal using correlation detection between pixels according to the present invention;

3 illustrates an embodiment of adding a pixel signal in the delay and adder of FIG.

4 is a conceptual diagram for explaining that the noise canceling apparatus according to the present invention is a kind of adaptive FIR filter.

5 is an embodiment showing the filter characteristics of the noise canceling apparatus according to the present invention,

FIG. 6 is a detailed block diagram detailing the delay and adder and filter of FIG.

7 is a detailed block diagram showing in detail the correlation detector and filter coefficient generator of FIG.

8 shows a partial sum of filters to explain that the coefficients of the filter equation according to the invention are determined.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise canceling device for a digital video signal, and more particularly to a noise control device suitable for integrated circuitry by removing noise by using correlation between pixels.

In general, a video signal is composed of a luminance signal Y, a color difference signal, and I and Q when using the color NTSC method. The chrominance signal is subsampled at the subsampling frequency and interleaved with the luminance signal. This subcarrier frequency f _sc is 3.57954 MHz.

Further, noise due to the digital sampling occurs between the noise referred to the highest frequency of the original signal f _∧, and when the sampling frequency f _s la, nf _{s ∧} ~nf -f _s + f _∧.

Therefore, when oversampling at four times the sampling frequency, since no noise is generated except a multiple of four of the oversampling frequency, the digital method generally eliminates noise by cutting the high range after oversampling.

Accordingly, in order to sample the video signal, the video signal is oversampled at a frequency four times the subcarrier frequency to prevent degradation of the video signal. Methods for digitizing video signals include a method of directly analog-to-digital converting a composite video signal having a mixture of luminance and chrominance signals, and a component method of separately converting luminance and chrominance signals separately. 8 bits is enough to digitize the video signal, even considering the dynamic characteristics.

A common method of removing noise of a digitally converted video signal is to use correlation between frames, between fields, or between lines. For example, as shown in FIG. 1, noise is removed by analyzing a correlation between a delayed previous field and a current field using a field memory.

1 is a block diagram showing a digital noise canceling apparatus according to US Patent 4,926,361 (1990.5.15) for removing noise using a frame or field memory according to the prior art. An m bit (usually m = 6 to 8) digital video signal is input to the input terminal 84 and enters the adder 81 and the subtractor 82. At this time, if the data input to ti is Xi, the Xi signal is subtracted from the Yi signal delayed by one frame and outputs a difference signal of (Yi-Xi). The secondary (Yi-Xi) signal is input to the variable coefficient multiplier 83 and the low level detector 87. The low level detector 87 detects the level of the (Yi-Xi) signal to control the coefficient K of the variable coefficient multiplier 83. The output of the variable coefficient multiplier 83 is input to the adder 81, added with other input signals by the adder 81, and output to the frame memory 85 and the output terminal 86.

The frame memory 85 serves as a kind of delayer to detect the correlation between the current frame and the previous frame. These conventional technologies have a disadvantage in that they are difficult to be monolithic because they are based on frame memory, which is a large memory, to analyze the correlation between frames or fields. That is, in the related art, in general, when detecting correlation, motion detection is used to determine and remove a signal component having a large motion as noise to prevent deterioration of contour, perform edge correction, and remove noise. In addition to the luminance signal Y, there is a function to remove noise of the color difference signals I and Q. However, since a large frame memory or a field memory is used, it cannot be embedded in an integrated circuit.

Accordingly, an object of the present invention is to eliminate noise of a digital video signal using correlation detection between pixels, which can simplify a circuit by using a frame (field) memory without using a frame (field) memory to solve the problems of the prior art. To provide.

In order to achieve the above object, the apparatus of the present invention is a noise removing device for removing noise in accordance with the degree of correlation between pixels in a digital image signal consisting of pixels sampled at least at the color carrier frequency,

A plurality of retarders for delaying the sampled pixel at least with a period of a color subcarrier and a plurality of adders for outputting a result of adding at least two of the inputs and outputs of the retarders, the pixel being an object of noise removal; A plurality of pixels corresponding to at least two sums of the plurality of pixels spaced apart at least by a period of a color subcarrier and at least two pixels among the noise removing target pixels and a plurality of pixels spaced at least at a period of a color subcarrier before and after Delay and addition means for generating them; Correlation detecting means for introducing the noise removing target pixel provided from the delay and adding means and a plurality of pixels spaced at least before and after the period of the color subcarrier to generate a correlation coefficient indicating a degree of correlation between pixels; Filter coefficient generating means for generating a plurality of filter coefficients for determining a selected combination of the plurality of addition signals provided from the delay and addition means in response to the correlation coefficient provided from the correlation detecting means; And selecting a combination according to filter coefficients provided by the filter coefficient generator from among the plurality of addition signals provided from the delay and addition means, and weight-adding the noise removing target pixel and the selected addition signals to remove noise. And filtering means for outputting a digital image signal composed of pixels.

Next, the apparatus of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram showing an apparatus for removing noise of an image signal using correlation detection between pixels according to the present invention, wherein a delay and adder 1, a correlation detector 3, a filter coefficient generator 4, and a filter 2 are shown. It is configured to include.

Noise removal device of the present invention, the color subcarrier to the four times the input 4 _fsc (14.318MHz) the 8-bit image signal sampled at a frequency, and by detecting a correlation between pixels in a non-adaptive switched by a coefficient corresponding to the degree of correlation Noise is removed by using a traversal filter (2). In addition, by adjusting the detection sensitivity for detecting the correlation coefficient according to the detection sensitivity control signal C inputted from an external microcomputer (not shown), the sensitivity to remove noise according to the type of video disc or the inner and outer periphery of the disc is controlled. can do.

That is, the delay and adder 1 inputs a digital image signal and delays it four times by four pixel clock periods corresponding to the period of the color subcarrier, so that each of the delay and adders 1 and 2 before and after the noise removal pixel signal is removed. The pixel signals of four pixel clock intervals are generated and added to each other, and the correlation detector 3 inputs the noise removing object pixel signal and the two pixel signals preceding the noise removing object from the delay and adder 1 to detect the detection sensitivity control signal ( According to C), the correlation of pixels is detected by adjusting the number of bits to be compared, and a correlation coefficient is output. Here, the pixel clock refers to a clock having a period corresponding to the interval between pixels. In the embodiment of the present invention, the pixel clock is a clock signal for oversampling.

The filter coefficient generator 4 inputs the correlation coefficient detected by the correlation detector 3 and inputs the previous correlation coefficient delayed by the 4-pixel clock period or the 8-pixel clock period to add the delay and the added output and noise of the adder 1. A filter coefficient selection signal for selecting one of the pixel signals to be removed is generated, and the filter 2 inputs an output added from the delay and adder 1 and a noise removal target pixel signal to be input from the filter coefficient generator 4. Noise is removed by selecting and adding the output corresponding to the filter coefficient selection signal.

FIG. 3 shows how the delay and adder 1 shown in FIG. 2 adds the respective pixels, where A0 is a pixel signal currently input and A4 is a 4-pixel clock than the pixel signal A0 currently input. A four-pixel delayed signal is input previously, A8 is an eight-pixel delayed signal input eight clocks earlier than the pixel signal A0 currently input, and A12 is twelve-pixel clocked ahead of the pixel signal A0 currently input. A 12-pixel delay signal is input, A16 is a 12-pixel delay signal input 16 pixels before the currently input pixel signal A0, and A16 is input by a 16-pixel clock before the pixel signal A0 currently input. It is a 16 pixel delay signal. Thus, as shown in FIG. 3, A0 + A8, A0 + A16, A4 + A8, A4 + A12, A8 + A12, and A8 + A16 are added.

FIG. 4 is a conceptual diagram for explaining that the apparatus of the present invention shown in FIG. 2 is a kind of Adaptive Finite Impulse Response (AFIR) filter. Digital signal processing has evolved to provide DSP chips with very high performance. However, digital filtering is the basis of digital signal processing. Digital filters are classified into IIR filters and FIRs. FIR filters have good phase characteristics. The key to implementing a digital filter is to determine the filter coefficients by considering how many of the filters will be satisfied. The filter equation of the present invention

Y (n) = a0 × (n) + a4 × (n-4) + a8 × (n-8) + a12 × (n-12) + a16 × n (n-16)... … … Equation 3

Where Y (n): filter output, x: filter input, a0, a4, a8, a12, a16: filter coefficient, and filter coefficients (a0, a4, a8, a12, a16) are filter coefficient generators. The filter coefficient value is adjusted in accordance with the output of (4).

5 is an embodiment schematically showing the filter characteristics of the noise canceling apparatus according to the present invention, where the horizontal axis represents frequency (Hz) and the vertical axis represents attenuation amount (dB). As shown in FIG. 5, the filter characteristic of the present invention passes the subcarrier frequency ( _rsc ) band having a direct current and a chrominance signal as it is, and mainly filters for noise included in the luminance signal (Y) component.

FIG. 6 is a detailed block diagram showing the delay and adder and the filter of FIG. 2 in detail. The delay and adder 1 includes the first delay unit 31, the second delay unit 32, and the third delay unit 33. , Fourth delayer 34, first adder 11, second adder 12, third adder 13, fourth adder 14, fifth adder 15, sixth adder 16 It is provided.

The filter 2 includes a first filter counter 41, a second filter counter 42, a third filter counter 43, a fourth filter counter 44, a seventh adder 17, and an eighth adder 18. And a ninth adder 19 and a tenth adder 20.

The delay and adder 1 inputs a digital video signal which is sampled from an external signal source (not shown) via an input terminal 5 with a sampling clock (4f _sc = 4 x 3.58 MHz = 14.32 MHz) and quantized to 8 bits.

Four delayed pixel signals A0 inputted to the input terminal 5 are delayed at intervals of four sampling periods (4f _sc ⁻¹ × 4 = 69.8ms × 4 = 279.2ms) in one delayer. 31, 32, 33, 34). The reason for delaying the 4-pixel clock cycle is because the phase of the signal changes by 90 ° during the modulation process of the color image signal, so that after the 4-pixel cycle, the phase becomes 360 °, so that the phase can be compared with the original signal.

The pixel signal output from the first delay unit 31 is delayed by a 4-pixel clock period from the pixel signal A0 currently input, corresponding to the 4-pixel delay signal A4 (the first delay pixel in the summary of the present invention). ), And the pixel signal output from the second delay unit 32 is delayed by an eight pixel clock period to become an eight pixel delay signal A8 (corresponding to the noise removing target pixel in the summary of the present invention). The pixel signal output from the three delay unit 33 is delayed by a period of 12 pixel clocks to become a 12 pixel delay signal A12 (corresponding to a third delay pixel in the summary of the present invention), and the fourth delay unit ( The pixel signal output from 34 is delayed by 16 pixel clock periods to become the 16 pixel delay signal A16 (corresponding to the fourth delayed pixel in the summary of the present invention). Among the delayed signals, the eight pixel delay signal A8, which is the output of the second delay unit 32, becomes the noise removing pixel signal.

The first adder 11 adds an 8-bit 4-pixel delay signal A4 and an 8-bit 12-pixel delay signal A12 to output 9 bits together with a carry output, and then excludes the LSB. The result of dividing by 2 is obtained to obtain an average value, and then output as a first addition signal to the first filter counter 41 and the second filter counter 42. The second adder 12 adds an 8-bit 4-pixel delay signal A4 and an 8-bit 8 pixel delay signal A8 to output 9 bits together with a carry output, and then shifts to 1 bit by excluding LSB. The average value is obtained by dividing by 2, and then output as a second addition signal to the first filter counter 41 and the second filter counter 42. The third adder 13 adds an 8-bit 8-pixel delay signal A8 and an 8-bit 12-pixel delay signal A12 to output 9 bits together with the carry output, and then excludes the LSB. The average value is obtained by dividing by 2, and then output as a third addition signal to the first filter counter 41 and the second filter counter 42.

The fourth adder 14 adds an 8-bit current input pixel signal A0 and an 8-bit 16-pixel delay signal A16 to output 9 bits together with a carry output, and then excludes the LSB. The average value is obtained by shifting the result by dividing by two, and then outputted as a fourth addition signal to the third filter counter 43 and the fourth filter counter 44. The fifth adder 14 adds an 8-bit currently input pixel signal A0 and an 8-bit 8 pixel delay signal A8 to output 9 bits together with a carry output, and then excludes the LSB. The average value is obtained by shifting the result by dividing by two, and then outputted as a fifth addition signal to the third filter counter 43 and the fourth filter counter 44. The sixth adder 16 adds an 8-bit 8-pixel delay signal A8 and an 8-bit 16-pixel delay signal 16 to output 9 bits together with a carry output, and then excludes the LSB. The average value is obtained by dividing by 2, and output to the third filter counter 43 and the fourth filter counter 44 as a sixth addition signal. Also, the pixel signal A0 currently input goes to the correlation detector 3 on the sinus line 100, the four pixel delay signal A4 goes to the correlation detector 3 on the signal line 101, and the eight pixel delay signal A8 is a signal line. At 102 we go to the correlation detector 3.

The filter 2 inputs the filter coefficient selection signal generated by the filter coefficient generator 4 to the signal line 110, changes the filter coefficients in the filter counters 41 to 44, and outputs a signal from which the noise is removed. The first filter counter 41 inputs a signal obtained by adding delayed pixel signals from the first adder 11, the second adder 12, and the third adder 13, which is an output of the second delay unit 32. An eight-pixel delay signal A8 is input, and one of four inputs is selected and output in accordance with the selection signal of the third group filter coefficient selection signals s9 to s12 input to the signal line 110. The second filter counter 42 inputs a signal obtained by adding delayed pixel signals from the first adder 11, the second adder 12, and the third adder 13, which is an output of the second delay unit 32. An eight-pixel delay signal A8 is input, and one of four inputs is selected and output in accordance with the selection signal of the fourth group filter coefficient selection signals s13 to s16 input to the signal line 110. The third filter counter 43 inputs a signal obtained by adding delayed pixel signals from the fourth adder 14, the fifth adder 15, and the sixth adder 16, and outputs the second delay unit 32. An eight-pixel delay signal A8 is input, and one of four inputs is selected and output in accordance with the selection signal of the first group filter coefficient selection signals s1 to s4 input to the signal line 110. The fourth filter counter 44 inputs a signal obtained by adding delayed pixel signals from the fourth adder 14, the fifth adder 15, and the sixth adder 16, and outputs the second delay unit 32. An eight-pixel delay signal A8 is input, and one of four inputs is selected and output in accordance with the selection signal of the second group filter coefficient selection signals s5 to s8 input to the signal line 110.

The seventh adder 17 adds and outputs a signal input from the first filter counter 41 and the second filter counter 42, and the ninth adder 19 inputs the output of the seventh adder 17. The eight pixel delay signal A8, which is the noise removing target, is input from the second delay unit 32 and added. The eighth adder 18 adds and outputs a signal input from the third filter counter 43 and the fourth filter counter 44, and the tenth adder 20 is a combination of the ninth adder 19 and the eighth adder. The output is input and added, and then output through the output terminal (6). The adders 17 to 20 used here add two 8-bit input signals, output 9 bits including carry, and then discard the LSB, which is shifted to the right and divided by 2 to output the average value. Be sure to In this way, the noise canceling function of the output signal has the effect of 0bB when the level difference between the pixels is large as a result of the experiment. This is for passing a synchronization signal, etc. It has a noise canceling function.

FIG. 7 is a detailed block diagram showing the second correlation detector and the filter coefficient generator in detail. The correlation detector 3 includes the eleventh adder 21, the twelfth adder 22, the first correlation detector 51, and the first correlation detector 51. A two-correlation detector 52, a third correlation detector 53, a fourth correlation detector 54, and a detection sensitivity controller 70 are provided, and the filter coefficient generator 4 includes a fifth delayer 35 and a sixth. The retarder 36, the seventh delay 37, the eighth delay 38, the first decoder 61, the second decoder 62, the third decoder 63, the fourth decoder 64 It is configured to include.

The correlation detector 3 detects correlation by comparing the level difference between the delay and delayed pixel signals input from the adder 1. That is, the eight pixel delay signal A8 that is the noise removing target pixel is subtracted from the pixel signal A0 that is currently input, and the eight pixel delay signal A8 that is the noise removing target pixel is subtracted from the four pixel delay signal A4. Is detected. In this case, the correlation detection method detects correlation by comparing bits of two pixels sequentially from MSBs of 8-bit pixel signals. For example, if the 8-pixel delay signal A8, which is the noise removing target pixel, is represented by Equation 1, and the currently input pixel signal A0 and the 4-pixel delay signal A4 can be expressed as Equation 2,

A8 = P ₇ P ₆ P ₅ P ₄ P ₃ P ₂ P ₁ P ₀ . … … … … … … … … … … … … … … … … … One

A0, A4 = Q ₇ Q ₆ Q ₅ Q ₄ Q _{3 2} Q ₁ Q ₀ . … … … … … … … … … … … … … … … 2

The correlation detector 3 is arranged between A _{7 to} A _x and B _{7 to} B _x (x = 0, 1, 2, 3) according to the detection sensitivity control signals C1 and C2 input from an external microcomputer (not shown). Compare the level difference. If the result of the comparison is the same, the filter coefficient generator 4 sends a signal to filter the noise removing target pixel, and at least one bit of the values (A _{7 to} A _x and B _{7 to} B _x ) between the pixels to be compared is different. In this case, the filter coefficient generator 4 is signaled to pass the noise removing target pixel. In other words, when the level difference between pixels is large, the signal having a large level difference, such as a synchronization signal, is mistaken for noise so as not to be processed. In addition, the detection sensitivity control signals C1 and C2 can control the noise removal sensitivity by determining the number of bits from the most significant bit MSB to the number of bits of the pixel to be compared. Table 1 below shows an example of determining the range of the comparison bit between the noise removing target pixel signal A8 and the pixel signals A0 and A4 according to the detection sensitivity control signals C1 and C2. It is shown.

As shown in Table 1 above, when the detection sensitivity control bits C1 and C2 are '0,' 0,0 ', the bits of the first and second expressions compare P7 to P0 and Q7 to Q0, and If 0, 1 ', bits of formula 1 and formula 2 compare P7 to P1 and Q7 to Q1. If' 1,0 ', bits of formula 1 and formula 2 to P7 to P2 and Q7 to Q2. In the case of '1, 1', the bits of the first expression and the second expression compare P7 to P3 and Q7 to Q3.

As described above, a method of determining a comparison range according to the detection sensitivity control signal may be variously implemented as necessary, and the above table is just one example.

The eleventh adder 21 inputs the 4-pixel delay signal A4 from the delay and adder 1 to the signal line 101, inputs the 8-pixel delay signal A8 to the signal line 102, inverts it, and subtracts it. Get the result.

The twelfth adder 22 inputs the pixel signal A0 currently input to the signal line 100, inputs the eight pixel delay signal A8 to the signal line 102, inverters, and adds the result.

The first correlation detector 51 inputs a signal A4-A8 obtained by subtracting the four-pixel delay signal A4 and the eight-pixel delay signal A8 from the eleventh adder 21 to the sixth bit to the second bit. The 5 bits are compared based on each other, the second bit is compared with the first bit according to the sensitivity control signals C1 and C2, and the first correlation coefficient signal COE1 is output.

That is, if the sensitivity control signals C1 and C2 are '0,1', the six bits are compared from the sixth bit to the second bit, and if the '1,0' is the seventh bit from the sixth bit to the zeroth bit, '1,1' compares only 5 bits from the sixth bit to the second bit. The second correlation detector 52 inputs a signal A4-A8 obtained by subtracting the four-pixel delay signal A4 and the eight-pixel delay signal A8 from the eleventh adder 21 to the sixth and fourth bits. The three bits are compared based on each other, the third bit is compared with the second bit according to the sensitivity control signals C1 and C2, and the second correlation coefficient signal COE2 is output. The third correlation detector 53 inputs a signal A0-A8 obtained by subtracting the pixel signal A0 and the eight pixel delay signal A8 currently input from the twelfth adder 22, and receives the sixth to third bits. The four bits are compared based on each other, the second bit is compared with the first bit according to the sensitivity control signals C1 and C2, and the third correlation coefficient signal COE3 is output.

The fourth correlation detector 54 inputs the signals A0-A8 obtained by subtracting the pixel signal A0 and the eight pixel delay signal A8 currently input from the twelfth adder 22 to input the sixth bit to the first bit. 6 bits are compared based on the above, 0th bits are compared according to the sensitivity control signals C1 and C2, and a fourth correlation coefficient signal COE4 is output. The detection sensitivity controller 70 inputs the detection sensitivity control signals C1 and C2 from the external microcomputer (not shown) to the signal line 103 and controls the correlation detection controllers 51 to 54 so that the lower four bits can be compared. To illustrate the generation of the correlation coefficient signals COE1 to COE4, the A8 signal represented by Equation 1 is called '11011001' (217), and the A0 or A4 signal represented by Equation 2 is represented by '11011110' (222). Let's do it. Comparing these two signals, it can be seen that A8A0 and A4. Inverters 21 and 22 add the inverted A8 signal and then add the inverted signal of the A8 signal to '00100110'. Now add these two signals up,

In the above added result, in case of A8A0, A4, the carry output is '1', and '0' is output from the most significant bit (MSB) to the bit with the same bit value.

In other words, if a comparison is made from P ₇ to P _x bits of Equation 1 (x = 0,1,2,3: determined by C1 and C2), '0' is output. In the above example, if A8 is compared with A0 and A4, the 8 bits from the MSB are the same, so it can be seen that the upper 5 bits of the addition result are '0'. In the first correlation counter 51, if C1 and C2 are '1'1 and only the upper 5 bits are compared, the first coefficient signal COE1 becomes'0', and if C1 and C2 are '1,0', The first coefficient signal COE1 becomes '1' by comparing up to 7 bits. Looking at the case of A8A0, A4 for better understanding, if A8 is '01011111' (95) and A0 or A4 is '01010100' (84), the result of adding A8 after inverting A8 in the adder (21,22) is

In case of A8A0, A4, carry output is '0' and '1' is outputted from the most significant bit (MSB) to the same bit.

That is, if P ₇ of Equation 1 to P _x bits are compared (x = 0,1,2,3: determined by C1, C2) and equal, '1' is output. In the above example, if A8 is compared with A0 and A4, the four bits from the MSB are the same, so it can be seen that the upper four bits of the addition result are '1'. In the fourth correlation counter 54, if the upper bits MSB are compared to six bits, the fourth coefficient signal COE4 becomes '0' because the addition result is the same as the upper four bits. If only the basic 4 bits are compared in the third correlation detector 53, the third coefficient signal COE3 becomes '1'. When comparing the sizes of A8, A0, and A4, the three cases are summarized. In case of A8A0 and A4, the carry output is '0', and the bits from MSB to Px = Qx are '1' and A8A0, A4. If the carry output is '1', the bits from MSB to Px = Qx are '0'. If A8 = A0 and A4, the carry output is '0' and all of MSB to LSB are '1'. In addition, without considering the detection sensitivity control signals (C1, C2), the case where the values of the coefficient signals (COE1 ~ COE4) has a value of '0' and '1' are summarized as shown in Table 2. In Table 2, the value of A8 represented by Equation 1 is referred to as 'P', and the value of A0 or A4 represented by Equation 2 is referred to as 'Q'.

The filter coefficient generator 4 inputs a result of comparing the eight pixel delay signal A8, which is the noise removing target pixel input from the correlation detector 3, with the pixel signal A0 or four pixel delay signal A4 currently input. Change the coefficient value of the filter.

The first decoder 61 inputs the first correlation coefficient signal COE1 from the first correlation detector 51, and inputs the first correlation coefficient signal COE1 to delay the delay signal by four pixel clocks 35. ) Inputs the first first correlation coefficient signal COE1 'to output the first group filter coefficient selection signals s1 to a4 for selecting one of the four inputs of the third filter counter 43. The second decoder 62 inputs the second correlation coefficient signal COE2 from the second correlation detector 52, and inputs the second correlation coefficient signal COE2 to delay the signal by four pixel clocks 36. ) Inputs the previous second 'correlation coefficient signal COE2' to output second group filter coefficient selection signals s5 to s8 for selecting one of the four inputs of the fourth filter counter 44. The third decoder 63 inputs the third correlation coefficient signal COE3 from the third correlation detector 53 and inputs the third correlation coefficient signal COE3 to delay the eighth clock by eight pixel clocks. The previous third correlation coefficient signal COE3 'is input from 37 to output the third group filter coefficient selection signals s9 to s12 for selecting one of the four inputs of the first filter counter 41. The fourth decoder 64 inputs the fourth correlation coefficient signal COE4 from the fourth correlation detector 54 and the eighth delay unit which delays the eighth correlation clock by inputting the fourth correlation coefficient signal COE4. The previous fourth correlation coefficient signal COE4 'is input from 38) to output fourth group filter coefficient selection signals s13 to s16 for selecting one of the four inputs of the second filter counter 42. The filter coefficient selection signals s1 to s16 are connected to the signal counters 41 to 44 of the filter 2 through the signal line 110.

An example of determining the values of the filter coefficient selection signals s1 to s16 according to the correlation coefficient signals COE1 to COE4 and COE1 'to COE4' input to the decoders 61 to 64 is shown in Tables 3 to 6 and the following. same.

8 shows a partial sum of filters to explain that the filter coefficients of the filter equation according to the present invention are determined.

The first and gate 101 receives a signal (A0 + A16) / 2 and is selected and output when s1 is '1', and is cut off when '0'. The second and gate 102 receives a signal (A0 + A8) / 2 and is selected and output when s2 is '1', and is cut off when '0'.

The three-and-gate 103 receives a signal (A8 + A16) / 2 and is selected and output when s3 is '1', and is cut off when '0'. The fourth and gate 104 receives the A8 signal and is selected and output when s4 is '1', and is cut off when '4'. The OR gate 117 outputs the logical sum of the outputs of the AND gates 101 to 104.

The fifth and gate 105 receives a signal (A0 + A16) / 2 and is selected and output when s5 is '1', and is cut off when '5'. The sixth and gate 106 inputs the signal (A0 + A8) / 2 and is selected and output when s6 is '1', and is cut off when '0'. The seventh gate 107 receives the signal (A8 + A16) / 2 and is selected and output when s7 is '1', and is cut off when '7'. The eighth and gate 108 inputs the A8 signal and is selected and output when s8 is '1', and is cut off when '8'. The oragate 118 logically sums the outputs of the AND gates 105 to 108 and outputs them.

The ninth end gate 109 is inputted with the signal (A4 + A12) / 2 and is selected and output when s9 is '1', and is cut off when '0'. The tenth and gate 110 receives a signal (A4 + A8) / 2 and is selected and output when s10 is '1', and is cut off when '0'. The eleventh and gate 111 inputs an (A8 + A12) / 2 signal and is selected and output when s11 is '1', and is cut off when '0'. The twelfth and gate 112 inputs the A8 signal and is selected and output when s12 is '1', and is cut off when '0'. The OR gate 119 logically sums the outputs of the AND gates 109 to 112 and outputs them.

The thirteenth and gate 113 inputs an (A4 + A12) / 2 signal and is selected and output when s13 is '1', and is cut off when '0'.

The fourteenth gate 114 is input when the signal (A4 + A8) / 2 is input and is output when s14 is '1', and is cut off when the signal is '0'. The fifteenth gate 115 receives (A8 + A12) / 2 signals and selects and outputs when s15 is '1', and is cut off when '0'. The sixteenth gate 116 inputs the A8 signal and is selected and output when s16 is '1', and is cut off when 's16'. The OR gate 120 logically sums the outputs of the AND gates 113 to 116 and outputs them. The eighth adder 18 to the tenth adder 20 are as described in the filter 2 of FIG. The filter coefficients of Equation 3, the equation of the filter, are determined by the sum of the signals selected by the filter coefficient selection signals s1 to s16. Since the filter wastewater selection signals s1 to s16 are determined by the correlation coefficient signals COE1 to 4, the relationship between the filter coefficients according to the correlation coefficient is summarized as follows. The filter coefficient a8 is a pair of the current correlation coefficient and the previous correlation coefficient {(COE1, COE1 '), (COE2, COE2'), (COE3, COE3 '), (COE4, COE4'),} equal to '1,1' It is determined by the number of cases. If there is no pair of '1,1', a8 is '5', if there is one a8 is '4', if there are two a8 is '3', if there are three a8 is '2', and all four Is '1,1', a8 is '1'. The filter coefficient a0 is determined by the current first correlation coefficient COE1 and the current second correlation coefficient COE2, and the filter coefficient a4 is determined by the current third correlation coefficient COE3 and the current fourth correlation coefficient COE4. Is determined. The filter coefficient a12 is determined by the previous third correlation coefficient COE3 'and the previous fourth correlation coefficient COE4', and the filter coefficient a16 is the previous first correlation coefficient COE1 'and the previous second correlation coefficient COE2' Is determined by

According to the present invention, a noise canceling function can be built into an integrated circuit without using a field memory or a frame memory, and an adaptive non-circulating digital filter allows up to 10dB of pass or noise suppression depending on the noise component of an input digital signal. By having the characteristic of can remove the noise of the video signal. Therefore, by using the present invention in the field of digital video signal processing, a clearer video signal can be obtained through a noise canceling function corresponding to the input video signal, and the circuit can be simplified by integrated circuit.

Claims (5)

A noise removing device for removing noise in accordance with a degree of correlation between pixels in a digital image signal composed of pixels sampled at least at a color carrier frequency, comprising: a plurality of delayers for delaying the sampled cycle at least by a period of the color carrier carrier; A plurality of adders for outputting at least two addition results among the inputs and outputs of the retarders, a pixel to be noise removed, a plurality of pixels spaced apart at least by a period of a color carrier, and the noise removal Delay and addition means for generating a plurality of addition signals corresponding to the sum of at least two of the plurality of pixels positioned at a distance apart from each other by at least the period of the color carriers before and after the target element; Correlation detecting means for introducing the noise removing target pixel provided from the delay and adding means and a plurality of pixels spaced at least before and after the period of a color carrier to generate a correlation coefficient indicating a degree of correlation between pixels; Filter coefficient generation means for generating a plurality of filter coefficient selection numbers for determining a selected combination of the plurality of addition signals provided from the delay and addition means in response to the correlation coefficient provided from the correlation detecting means; And selecting a combination according to filter coefficient selection signals provided by the filter coefficient generating means from among the plurality of addition signals provided from the delay and addition means, and weight-adding the noise removing target pixel and the selected addition signals to add noise. And a filtering means for outputting a digital image signal composed of the removed pixels. 2. The apparatus of claim 1, wherein the delay and addition means are connected in series, each of which delays a pixel input thereto at least by a period of a color carrier so that a period of the first delayed pixel and a color carrier can be set by a period of a color carrier from a pixel currently input. Four delayers each generating a noise removing target pixel delayed by twice the period, a third delayed pixel delayed by three times the period of the color carrier, and a fourth delayed pixel delayed by four times the period; A first adder for outputting a result of the addition of the first delayed pixel and the third delayed pixel as a first addition signal; A second adder for outputting the added result of the noise removing target pixel of the first delayed pixel as a second addition signal; A third adder for outputting the added result of the noise removing target pixel and the fourth delayed pixel as a third addition signal; A fourth adder for outputting a result of the addition of the current input pixel and the fourth delayed pixel input to the first delay unit as a fourth addition signal; A fifth adder which outputs the added result of the noise removing target pixel and the fourth delayed pixel as a fifth adding signal; And a sixth adder for outputting a result of the addition of the noise removing target pixel and the fourth delayed pixel as a sixth addition signal. 3. The apparatus of claim 2, wherein the correlation detecting means comprises: an eleventh adder for adding the first delayed pixel and the third delayed pixel; A twelfth adder for adding the currently input pixel and the noise removing target pixel; A detection sensitivity controller for controlling a degree of detecting correlation between pixel signals in response to a detection sensitivity control signal applied from the outside; A first correlation detector configured to input an output of the eleventh adder and an output of the detection sensitivity controller to detect correlation between pixels and output the first correlation coefficient as a first correlation coefficient; A second correlation detector configured to input an output of the eleventh adder and an output of the detection sensitivity controller to detect a correlation between pixels and output the second correlation coefficient as a second correlation coefficient; And a fourth correlation detector for inputting an output of the twelfth adder and an output of the detection sensitivity controller to detect correlation between pixels and output the fourth correlation coefficient as a fourth correlation coefficient. 4. The apparatus of claim 3, wherein the filter coefficient generating means comprises: first decoding means for introducing the first correlation coefficient and a delay of it by four pixels and outputting the first filter coefficient selection signal; Second decoding means for introducing the second correlation coefficient and delaying it by four pixels and outputting the second filter coefficient selection signal; Third decoding means for introducing the third correlation coefficient and the delay of it by four pixels and outputting the third filter coefficient selection signal; And fourth decoding means for introducing the delay of the fourth correlation and the four by four pixels and outputting the fifth filter coefficient selection signal. 5. The apparatus of claim 4, wherein the filtering means comprises: a first filter counter selectively selecting the first addition signal, the second addition signal, the third addition signal and the noise removing pixel according to the first filter coefficient selection signal; A second filter counter selectively outputting the first addition signal, the second addition signal, and the noise removing target pixel according to the second filter coefficient selection signal; A seventh adder for adding the output of the first filter counter and the output of the second filter counter; A ninth adder configured to add the output of the seventh adder and the noise removing target pixel; A third filter counter selectively outputting the fourth addition signal, the fifth addition signal, the sixth addition signal, and the noise removing target pixel according to the third filter coefficient selection signal; A fourth filter counter selectively outputting the fourth addition signal, the fifth addition signal, the sixth addition signal, and the noise removing target pixel according to the fourth filter coefficient selection signal; An eighth adder configured to add an output of the third filter counter and an output of the fourth filter counter; And a tenth adder for outputting the digital image data from which the noise is removed by adding the output of the ninth adder and the output of the eighth adder.