KR960009935B1 - Logic analizer apparatus for duo-binary signal - Google Patents

Abstract

two comparative operators (1) for comparing n input signals simultaneously received from each channel with a reference voltage; a memorizing start-up condition detector (5) for comparing the two output signals from the comparative operators (1) with a predetermined memorizing start-up condition to generate a memorizing start-up signal; a sample/hold means (2) for regulating the output of the comparative operators (1) in accord with the predetermined memorizing start-up condition; a code and logic determining means (4) for determining the code and logic; a memory (6) for storing the duo-binary-signals of each channel; and a display (7) for displaying the signal stored in the memory (6).

Description

Logic Analyzer Device for Duobinary Signals

1 is a block diagram of a prior art.

2 is an exemplary waveform diagram of binary and duobinary numbers.

3 is a block diagram of the present invention.

4 is a diagram illustrating a configuration of a sign and logic determination unit.

5 is an exemplary configuration diagram of a storage unit for a duo binary signal.

* Explanation of symbols for main parts of the drawings

1: comparison operation unit 1-1 to 1-n: comparison operation unit

2: Sample / Hold Part 3: Oscillator

4: Sign / Logic Decision Unit 4-1 to 4-n: Sign / Logic Decision Machine

5: Storage start condition detection unit 6: Duo binary signal storage unit

7: display unit.

The present invention relates to an apparatus for storing and displaying duobinary signals.

Referring to FIG. 1, the logic analyzer is a device that receives, stores, and displays a digital signal, which is essential for the development of a device using a digital signal such as a computer, an electronic calculator, a data communication device, and an HDTV. to be. In the case of the oscilloscope, you can see the detailed shape of the waveform because it shows the analog value of the signal as it is, but in the case of the logic analyzer, you can set an arbitrary threshold value so that if the value is higher than the reference value, the high value is low and the low value is low The oscilloscope usually has two channels and at most four channels, while the logic analyzer has dozens or hundreds of channels, so it is easy to use digital signals of multiple channels. Can be observed. N signals are input at the same time and the signals are compared with a preset reference voltage. At this time, if it is higher than the reference voltage, it becomes low when it is high and low, and it is converted into a binary value and has no value other than these two values.

The values obtained here are also compared with the preset storage start condition and are sequentially stored in the storage unit when the storage start signal is generated. At this time, the time interval of the stored signal is adjusted to meet the preset condition in the sampling and holding unit so that it is accurately transmitted to the storage unit. The previous signal stored in this way is displayed on the screen controlled by the user as desired. As such, the logic control analyzer can store and display signals accurately for binary signals but cannot process them for duo binary signals, and the binary binary signals themselves have binary values but three values. In other words, as shown in Table 1>, the value of low in binary number has the value of low in the duo binary, but the value of high is expressed as + high and-high.

TABLE 1

And, Figure 2 shows the waveform of each signal. As described above, when a duo binary signal is measured by a general logic analyzer, any one of + high and -high signals may go to a low signal.

In order to solve the above problems, an object of the present invention is to provide a logic analyzer device for a duobinary that can store a duobinary signal.

In order to achieve the above object, the present invention, the comparison operation means consisting of two comparison operators for inputting the signal input of each channel to the positive input terminal at the same time and the reference input to the negative input terminal and outputs after the comparison operation; Storage time condition detection means for generating a storage start signal by comparing the two output signals from said comparison calculation means with a storage start condition for generating a storage start signal, and said comparison operation; A sample / hold means for adjusting the output of the means according to a preset condition according to the storage start signal of the storage start condition detecting means, and the output of the sample / hold means to determine the sign and logic to determine the corresponding output. Code and logic determining means for generating, and a duo-biner of each channel determined by the code and logic determining means Comprises a duobinary signal storage means for storing a signal, display means for displaying a signal that has been stored and the sample / hold means to said duobinary signal storage means.

Hereinafter, the present invention will be described in detail with reference to FIG. 3.

3 is a block diagram of a logic analyzer for a duobinary signal according to the present invention.

In the drawing, 1 is a comparison operator, 1-1 to 1-n is a comparison operator, 2 is a sample / hold unit, 3 is an oscillator, 4 is a sign / logic determination unit, 5 is a storage start condition detection unit, 6 is a duo binary signal. The storage part 7 represents a display part, respectively.

As shown in the figure, a comparison operation unit 1 composed of two comparators which input n signal inputs of each channel to the positive input terminal at the same time and receive a reference voltage as the sub-input terminal and output the result after the comparison operation; A storage start condition detecting unit 5 which compares two output signals from the comparison calculating unit 1 with a preset storage start condition and generates a storage start signal, and outputs the output of the comparison calculating unit 1 to the storage starting condition; According to the storage start signal of the detector 5, the sample / hold unit 2 is adjusted according to a predetermined condition and the output of the sample / hold unit 2 is applied to determine the sign and logic to determine the corresponding output. A duobinary signal storage section 6 for storing a duobinary signal of each channel determined by the generated sign and logic decision section 4, the sample / hold section 2 and the duobinary signal storage section ( A display unit 7 for displaying a signal stored in 6), an oscillator 3 for providing a clock to the sample / hold unit 2, and the dual-binar signal storage unit 6; .

That is, the signals of each of the n channels are input to two comparators so that the reference comparator 1 is applied to the first comparator and the reference voltage 2 is applied to the other comparator, and the reference voltage 1 is a value between + high and low (e.g., (( + High) + low) / 2) and reference voltage 2 applies a value between low and -high (e.g., (low + (-high) / 2) to convert the input signal into a duo binary signal. The converted signal is applied to the sign and logic decision unit 4 when the storage start condition in the storage start conditional unit 5 is detected across the sample / hold unit 2. It is + high, low, and -high. It recognizes the three states of, and the truth table of codes and logic is shown in Table 2 below.

TABLE 2

By storing the sign signal and the logic signal as described above, the form of the duobinary signal can be stored.

The duobinary signal storage section stores two signals, the configuration of which is shown in FIG.

5 is a detailed configuration diagram of a storage unit for a duo binary signal.

As shown in the figure, in selecting and determining a sign and a logic, n flip-flops 51 are formed in each sign or logic. The operation of the individual flip-flops 51 is as described above, and details thereof are conventional in the art, and description thereof will be omitted.

Therefore, there is an effect that it is possible to store, read and display the duobinary signal.

Claims (1)

A comparison calculation means (1) consisting of two comparison calculators for inputting the signal inputs of each channel to the positive input terminal at the same time and receiving a reference voltage as the negative input terminal and outputting the result of comparison operation; Storage start condition detecting means (5) for generating a storage start signal by comparing two output signals from the < RTI ID = 0.0 > preliminary < / RTI > storage start condition, and outputting the output of the comparison calculation means (1) to the storage start condition detecting means ( 5) a sample / hold means 2 for adjusting to a predetermined condition according to the storage start signal of 5) and an output of the sample / hold means 2 to determine a sign and a logic to generate respective corresponding outputs. Sign and logic determining means (4), duo binary signal storage means (6) for storing the duo binary signals of each channel determined by said sign and logic determination means (4), and said sample / hold means (2) and display means (7) for displaying a signal stored in said storage means (6) for said duobinary signal.