JPS62174662A - Logic analyzer - Google Patents

Abstract

PURPOSE:To display the rough inclination of much data exceeding the resolution of a display device by sectioning data of a display device by the specific number of samples and counting and quantizing specific waveform information included therein. CONSTITUTION:A controller 1 consists of a dividing means 1A, a measuring means 1B, and a quantizing means 1C and utilizes the arithmetic functions of a CPU to perform processing. The means 1A fetches timing wave data of a set number of samples from a data storage device 2 at every time. This data is inputted to the means 1B and included specific waveform information, i.e. the number of samples in, for example, an H-logic state is counted. Those counted values are quantized into a specific number of codes with a set quantization number by the means IC. Those quantized codes are inputted to a character generator 7, converted into display patterns made to correspond to the respective quantized codes, and supplied as display patterns to the display device 3. Thus, the distribution of the specific waveform information included in the timing waveform data is displayed, so the inclination of the whole in a long sequence is displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a logic analyzer used for analyzing the operation of various digital circuits.

``Prior art'' The waveform data of each part of the digital circuit is stored in a data storage device (=
A logic analyzer is a device that analyzes the operating timing of a circuit by displaying the timing waveform data captured in a data storage device on a display such as a cathode ray tube.

FIG. 5 shows the configuration of a conventional logic analyzer. In the figure, numeral 1 indicates a controller composed of, for example, a microcomputer. A data storage device 2, a display device 3, and a keyboard 4 are connected to this controller 1 by a pass line 5.

The data storage device 2 has a plurality of input terminals CH1, CH2...
... CHn, and these plural input terminals CH1 to CH
Timing waveform data of each part of the digital circuit to be tested is input to n.

The controller (3) performs control to take input timing waveform data into the data storage device 2 and control to transfer data from the data storage device 2 to the display device 3.

The keyboard 4 is used to set data acquisition conditions, such as the acquisition clock frequency and the number of data samples.

When the data storage device 2 receives data for the set number of samples, the controller 1 reads out the data.

The data is transferred to the display 3 and a plurality of timing waveforms are displayed.

A recent trend in logic analyzers is that the capacity of the data storage device 2 that takes in data is increasing. The capacity of the data storage device 2 can be divided into the channel direction and the time axis direction.

Channel direction is the number of waveform data to be captured, usually 8~
Selected as 16 channels. On the other hand, the time axis direction corresponds to the number of samples of data to be taken in, and the larger the number, the better the resolution of the waveform data can be displayed on the display 3. It is also possible to capture timing data from the beginning to the end of a long sequence. For these reasons, there is a tendency to increase the capacity of the data storage device 2 in the time axis direction.

By the way, the number of dots that can be displayed in the horizontal direction on one display 3 (in the case of a cathode ray tube) is 1 for the capacity of the data storage device 2 in the time axis direction (hereinafter referred to as the number of samples).
With approximately 000 dots, data of approximately 500 samples can be displayed. The capacity of the data storage device 2 is several to several hundred times larger than the number of samples that can be displayed.

By providing such a large-capacity data storage device 2, timing waveform data can be captured with good resolution, as described above, and a long series of timing waveform data can all be captured.

"The problem that the invention attempts to solve" There is a request to display the entire long sequence.

Conventionally, in response to such a request, the data was thinned out and displayed every appropriate number of samples from all the data imported into the data storage 2, or all the data was transferred to the display 3 (=transferred,
All the data is displayed on the display 3.

When data is thinned out and displayed (= has the drawback that the displayed waveform is different from the original waveform, resulting in a lack of reliability.Also, since it only invades the data storage 2, the changes on the time axis There is a disadvantage that it cannot be read even if it is a trend.

An object of the present invention is to provide a logic analyzer that can display a rough tendency of the data when displaying a large amount of data that exceeds the resolution of the display.

"Means for Solving the Problem" In the present invention, in a logic analyzer configured to transfer timing waveform data captured in a data storage device to a display and display the timing waveform data on the display, data A dividing means for dividing the timing waveform data taken into the memory into a plurality of sections having a desired number of samples, and a counting means for counting the number of samples having specific information existing in each of the plurality of divided sections. , a quantization means that quantizes the numerical value counted by the counting means into a plurality of codes, and a display pattern assigned to each quantized code is stored, and when the quantized code is given, the code is A display device (=a character generator that outputs a corresponding display pattern) is attached.

According to the configuration of the present invention, timing waveform data arranged in the time axis direction is divided into a plurality of samples, and the number of samples having specific information, such as H logic information, included in the divided area is counted. .

The count value is quantized into multiple codes. For example, if the total number of samples in the divided area is n, then n
is divided into K sections and encoded.

- For example, the total number of samples is ioo, and the number of i-childs is K = 4. If the number of samples with H logic is i, then i=0
quantize the state of 7
The state of 5<i<100 is quantized to code E, and 1=loO
The state of is quantized by code F (double quantization.

The quantized codes A-F are given to the character generator, and the character generator outputs display patterns assigned to the codes A-F.

The display pattern has a single length in the time axis direction.

It can be set to have information 2 corresponding to the number i of H logic, for example, an amplitude value. In other words, for example, if there are 100 H logics in 100 samples width (corresponding to quantization code F)
If the amplitude of the display pattern of symbol A is 100 inches, the amplitude of the display pattern of code A is OS.

The amplitude of the display pattern of code B can be set to 20%, the amplitude of the display pattern of code C can be set to 40%, the amplitude of the display pattern of code E can be set to 60%, and the amplitude of the display pattern of code E can be set to 80%. can.

In this way, by quantizing all the data taken into the data storage device and converting it into a display pattern (= conversion), it is possible to display l[- of all the data on the display.

In particular, it is possible to display the distribution of H logic waveforms within long sequences.

Further, when counting 4-constant information in each section, the configuration may be such that the rising edge or falling edge of the logical waveform is counted. When the rising or falling edges of a signal are counted in this way, it is possible to display the frequency distribution in which the waveform changes.

"Embodiment" FIG. 1 shows an embodiment of the present invention. 1 in the figure is a controller,
2 is a data storage device, 3 is a display device, 4 is a keyboard/eboard,
5: The points indicating bus lines are the same as in the conventional one.

In this invention, a dividing means divides the timing waveform data taken into the data storage device 2 into a plurality of sections each having a desired number of samples.

and a counting means for counting the number of samples having specific information existing in each of the plurality of divisions.

and quantization means for quantizing the numerical value counted by the counting means into a plurality of codes.

A character generator is provided which stores each quantized code (2 assignment) display pattern and outputs a display pattern corresponding to the code by giving the quantized code. A certain dividing means and counting means,
In this example, the quantization means is provided inside the controller l. In the figure, IA is a dividing means, IB is a counting hand [1, and IC is a quantizing means. These dividing means IA, counting hand 191
B. The quantization means IC actually uses the arithmetic function of a microcomputer and processes it by software:
I can do it. The outline of the program is shown in Figure 2 (=flowchart).

The dividing means IA takes in timing waveform data from the data storage 2 by a set number of samples.

Counters 1 & IB count specific waveform information included in this timing waveform data, for example, the number of samples in the H logic state.

The quantization means 1C is a counting means! Quantize i into (K+2) codes using the set quantization number.

The quantization code obtained by encoding is given to the character generator 7 via the display storage 6. The character generator 7 is provided with display patterns corresponding to the quantization number K. The number of display patterns actually displayed is (K+2), but the display pattern with an amplitude of Ochi and the display pattern with an amplitude of 100%
The display pattern is fixed. Therefore, the range between 0 and 100'% is equally divided by (K+1) and displayed using K display patterns.

For example, when =4, as shown in Figure 3 (2), display pattern 8 with amplitude value 0, display pattern PB with amplitude value 20, display pattern pc with amplitude 40%, amplitude fi!
When a display pattern PD of 60%, a display pattern PE of amplitude iii 80chi, and a display pattern PF of 100% amplitude are prepared, and any of the quantization codes A to F is entered manually, the u digitization code 'FiA -F- Display pattern PA with two pairs of windows
= PF is read out, and this display pattern PA~pF is given to the display 3 to be displayed.

FIG. 4 shows an example of the display. This example shows a case where eight channels of timing waveform data are displayed.

"Operations and Effects of the Invention" As explained above (2) According to this invention (2), a large amount of data exceeding the display resolution of the display 3 is divided into a predetermined number of samples, and specific waveform information contained in the divided data is It counts, quantizes the counted value, and converts the resulting quantization code into a display pattern and displays it. Therefore, it is possible to display the distribution of specific waveform information included in timing waveform data. can.

Therefore, the overall trend of a long sequence can be displayed, which is effective for timing analysis.

"Modified Embodiment of the Invention" In the above description, a case has been described in which the specific waveform information included in the two-divided area is set to H logic for each predetermined number of samples; however, it is also possible to count the number of rises and falls of the waveform. good. Furthermore, although an example has been described in which the display patterns Pa to PF are distinguished by amplitude values (:), the display patterns may also be distinguished by differences in color, black and white shading, hatching, etc.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining an embodiment of the present invention, Fig. 2 is a flowchart for explaining the outline of a program that constitutes the main part of this invention, and Fig. 3 is a diagram of a display pattern. The fourth figure is a waveform diagram showing an example of the display of the logic analyzer according to the present invention. FIG. 5 is a block diagram showing the configuration of the conventional logic analyzer. ■=controller, IA: dividing means 51B two counting means, IC:
Quantization means, 2: data storage, 3: display, 4: keyboard, 5: bus line, 6: display storage, 7: character generator. Patent applicant: Atopan Test Co., Ltd.
Person Takuo Kusano 1 Illustration 3 Figure 2

Claims (1)

[Claims] (1) A: In a logic analyzer in which the timing waveform data taken into the data storage device is fed to the display via the controller and the timing waveform data is displayed on the display; B. The timing waveform data taken into the data storage device A dividing means for dividing the data into a plurality of sections having a desired number of samples; C. A counting means for counting specific waveform information included in the sections divided into the desired number of samples; D. quantization means for quantizing a numerical value into a plurality of quantization codes;
A logic analyzer comprising: character generation means for providing a display pattern to the display;