KR960009665B1 - Data multiple transfer cycle implementing apparatus using hardware - Google Patents
Data multiple transfer cycle implementing apparatus using hardwareInfo
- Publication number
- KR960009665B1 KR960009665B1 KR94029084A KR930029084A KR960009665B1 KR 960009665 B1 KR960009665 B1 KR 960009665B1 KR 94029084 A KR94029084 A KR 94029084A KR 930029084 A KR930029084 A KR 930029084A KR 960009665 B1 KR960009665 B1 KR 960009665B1
- Authority
- KR
- South Korea
- Prior art keywords
- signals
- hardware
- signal
- transfer cycle
- multiple transfer
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Communication Control (AREA)
Abstract
a signal converter(8) for generating firsttr* and scndtr* signals which indicate a number of transmissions if a data is larger than port sizes or does not aligned to a port size width when accessing to 4 byte or 2 byte port communication controller; a state controller(9) for controlling transmitting time using dtack*, berr*, vmbreq*, and vmbgr* signals; a decoder for generating a transmission ending signal(ldtack*) and an error signal(lberr*) using Tout[3:0 (transmitting starting time control signal), vmiack*, be*[7:0 , and r/w signals, and driving buffer in a certain direction; and buffers for data transmission.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94029084A KR960009665B1 (en) | 1993-12-22 | 1993-12-22 | Data multiple transfer cycle implementing apparatus using hardware |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR94029084A KR960009665B1 (en) | 1993-12-22 | 1993-12-22 | Data multiple transfer cycle implementing apparatus using hardware |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950022341A KR950022341A (en) | 1995-07-28 |
KR960009665B1 true KR960009665B1 (en) | 1996-07-23 |
Family
ID=19397264
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR94029084A KR960009665B1 (en) | 1993-12-22 | 1993-12-22 | Data multiple transfer cycle implementing apparatus using hardware |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960009665B1 (en) |
-
1993
- 1993-12-22 KR KR94029084A patent/KR960009665B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950022341A (en) | 1995-07-28 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |