KR960009660B1 - The data coincidence maintenance device between the on-chip cache and the external cache - Google Patents

The data coincidence maintenance device between the on-chip cache and the external cache Download PDF

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Publication number
KR960009660B1
KR960009660B1 KR94011544A KR19940011544A KR960009660B1 KR 960009660 B1 KR960009660 B1 KR 960009660B1 KR 94011544 A KR94011544 A KR 94011544A KR 19940011544 A KR19940011544 A KR 19940011544A KR 960009660 B1 KR960009660 B1 KR 960009660B1
Authority
KR
South Korea
Prior art keywords
cache
processor
maintenance device
snoop
address
Prior art date
Application number
KR94011544A
Other languages
Korean (ko)
Other versions
KR950033845A (en
Inventor
Rae-Sang Jang
Original Assignee
Daewoo Telecom Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Daewoo Telecom Co Ltd filed Critical Daewoo Telecom Co Ltd
Priority to KR94011544A priority Critical patent/KR960009660B1/en
Publication of KR950033845A publication Critical patent/KR950033845A/en
Application granted granted Critical
Publication of KR960009660B1 publication Critical patent/KR960009660B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

a process bus arbitrating unit(10) for controlling a processor bus cycle; a que(11) for storing an address to be snooped by a processor(1); an external tag RAM(12) for substituting the process operation when the processor need to snoop; an address module(14) for supplying an address needed to snoop; a tag controller(13) for generating control signal of the processor arbitrating unit, the que and the snoop; and a bus interface(15) for interfacing a system bus and an address module.
KR94011544A 1994-05-26 1994-05-26 The data coincidence maintenance device between the on-chip cache and the external cache KR960009660B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94011544A KR960009660B1 (en) 1994-05-26 1994-05-26 The data coincidence maintenance device between the on-chip cache and the external cache

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR94011544A KR960009660B1 (en) 1994-05-26 1994-05-26 The data coincidence maintenance device between the on-chip cache and the external cache

Publications (2)

Publication Number Publication Date
KR950033845A KR950033845A (en) 1995-12-26
KR960009660B1 true KR960009660B1 (en) 1996-07-23

Family

ID=19383844

Family Applications (1)

Application Number Title Priority Date Filing Date
KR94011544A KR960009660B1 (en) 1994-05-26 1994-05-26 The data coincidence maintenance device between the on-chip cache and the external cache

Country Status (1)

Country Link
KR (1) KR960009660B1 (en)

Also Published As

Publication number Publication date
KR950033845A (en) 1995-12-26

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