KR960009537B1 - Circuit for detecting phase transformation - Google Patents

Circuit for detecting phase transformation Download PDF

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Publication number
KR960009537B1
KR960009537B1 KR93028941A KR930028941A KR960009537B1 KR 960009537 B1 KR960009537 B1 KR 960009537B1 KR 93028941 A KR93028941 A KR 93028941A KR 930028941 A KR930028941 A KR 930028941A KR 960009537 B1 KR960009537 B1 KR 960009537B1
Authority
KR
South Korea
Prior art keywords
output
address
data
latch
incosh
Prior art date
Application number
KR93028941A
Other languages
Korean (ko)
Other versions
KR950022355A (en
Inventor
Jin-Ho Cho
Chol-Sik Pyo
Jae-Ik Choe
Original Assignee
Korea Electronics Telecomm
Korea Telecommunication
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Electronics Telecomm, Korea Telecommunication filed Critical Korea Electronics Telecomm
Priority to KR93028941A priority Critical patent/KR960009537B1/en
Publication of KR950022355A publication Critical patent/KR950022355A/en
Application granted granted Critical
Publication of KR960009537B1 publication Critical patent/KR960009537B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The circuit includes an ADC(1) for digitizing an input data; RAM(2) for storing the data; a MAC (Multiple & Accumulator) (4) for correlated accumulation of an output and input data; a coefficient PROM(3) for sending the data to the MAC after sampling a 1331/3Kb/s analog signal; the first. output latch(5) for generating an output whenever a PROM output is matched to a counter setting value; an input latch(6) for assigning the starting address; a counter(7) for counting an address; first adder for increasing the address; Incosh PROM(9) for inputting Incosh function value as an address after transforming the output of the 1st output latch, or for outputting an Incosh value corresponding to the address; a frame accumulator(12) for adding and accumulating the data; 2nd output latch(13) for latching an output of the frame accumulator; thereby improving a phase change detection.
KR93028941A 1993-12-21 1993-12-21 Circuit for detecting phase transformation KR960009537B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93028941A KR960009537B1 (en) 1993-12-21 1993-12-21 Circuit for detecting phase transformation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93028941A KR960009537B1 (en) 1993-12-21 1993-12-21 Circuit for detecting phase transformation

Publications (2)

Publication Number Publication Date
KR950022355A KR950022355A (en) 1995-07-28
KR960009537B1 true KR960009537B1 (en) 1996-07-20

Family

ID=19372034

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93028941A KR960009537B1 (en) 1993-12-21 1993-12-21 Circuit for detecting phase transformation

Country Status (1)

Country Link
KR (1) KR960009537B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100640432B1 (en) * 2002-10-09 2006-10-30 삼성전자주식회사 Method of phase demodulation for phase error suppressing of communication signal

Also Published As

Publication number Publication date
KR950022355A (en) 1995-07-28

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