KR960009219A - Method of manufacturing thin film transistor - Google Patents

Method of manufacturing thin film transistor Download PDF

Info

Publication number
KR960009219A
KR960009219A KR1019940021064A KR19940021064A KR960009219A KR 960009219 A KR960009219 A KR 960009219A KR 1019940021064 A KR1019940021064 A KR 1019940021064A KR 19940021064 A KR19940021064 A KR 19940021064A KR 960009219 A KR960009219 A KR 960009219A
Authority
KR
South Korea
Prior art keywords
forming
thin film
substrate
film transistor
gate electrode
Prior art date
Application number
KR1019940021064A
Other languages
Korean (ko)
Other versions
KR0140635B1 (en
Inventor
윤현도
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940021064A priority Critical patent/KR0140635B1/en
Publication of KR960009219A publication Critical patent/KR960009219A/en
Application granted granted Critical
Publication of KR0140635B1 publication Critical patent/KR0140635B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402Field plates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 박막트랜지스터 누설전류를 감소시키기 위한 것이다.The present invention relates to a method for manufacturing a thin film transistor, and to reduce the leakage current of the thin film transistor.

본 발명은 기판상에 형성된 절연층상부에 게이트전극을 형성하는 공정과, 상기 게이트전극이 형성된 기판 전면에 게이트절연막을 형성하는 공정, 상기 게이트전극 측면의 게이트절연막상에 도전 물질로 된 전계차폐층을 형성하는 공정, 기판 전면에 폴리실리콘층을 형성하는 공정, 및 상기 폴리실리콘층 소정부위에 불순물을 선택적으로 도핑하여 소오스영역과 드레인영역을 형성하는 공정을 포함하여 이루어지는 박막트랜지스터 제조방법을 제공함으로써 전계차폐층이 박막트랜지스터 OFF상태에서 게이트로부터 드레인까지의 전계를 차폐시키는 역할을 하도록 하여 드레인접합부에서의 전자-정공쌍의 생성율을 저하시키고 이에 따른 누설전류가 감소되도록 한다.The present invention provides a process of forming a gate electrode on an insulating layer formed on a substrate, a process of forming a gate insulating film on the entire surface of the substrate on which the gate electrode is formed, and an electric field shielding layer of a conductive material on the gate insulating film on the side of the gate electrode. Forming a polysilicon layer on the entire surface of the substrate; and selectively forming a source region and a drain region by selectively doping impurities into a predetermined portion of the polysilicon layer. The field shielding layer serves to shield the electric field from the gate to the drain in the OFF state of the thin film transistor, thereby reducing the generation rate of the electron-hole pair in the drain junction and thus reducing the leakage current.

Description

박막트랜지스터 제조방법Method of manufacturing thin film transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 박막트랜지스터 단면구조도1 is a cross-sectional structure of a conventional thin film transistor

제2도는 본 발명에 의한 박막트랜지스터 제조방법을 도시한 공정순서도2 is a process flowchart showing a method of manufacturing a thin film transistor according to the present invention.

Claims (2)

기판상에 형성된 절연층상부에 게이트전극을 형성하는 공정과,Forming a gate electrode on the insulating layer formed on the substrate; 상기 게이트전극이 형성된 기판 전면에 게이트절연막을 형성하는 공정,Forming a gate insulating film on an entire surface of the substrate on which the gate electrode is formed; 상기 게이트전극 측면의 게이트절연막상에 도전물질로 된 전계차폐층을 형성하는 공정,Forming an electric field shielding layer of a conductive material on the gate insulating film on the side of the gate electrode; 기판 전면에 폴리실리콘층을 형성하는 공정, 및Forming a polysilicon layer on the entire surface of the substrate, and 상기 폴리실리콘층 소정부위에 불순물을 선택적으로 도핑하여 소오스영역과 드레인영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 박막트랜지스터 제조방법.And forming a source region and a drain region by selectively doping an impurity in a predetermined portion of the polysilicon layer. 제1항에 있어서, 상기 전계 차폐층은 상기게이트절연막상부에 폴리실리콘을 증착한 후, 이를 이방성식각하여 형성하는 것을 특징으로 하는 박막트랜지스터 제조방법.The method of claim 1, wherein the electric field shielding layer is formed by depositing polysilicon on the gate insulating layer and then anisotropically etching it. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940021064A 1994-08-25 1994-08-25 Thin film transistor KR0140635B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940021064A KR0140635B1 (en) 1994-08-25 1994-08-25 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940021064A KR0140635B1 (en) 1994-08-25 1994-08-25 Thin film transistor

Publications (2)

Publication Number Publication Date
KR960009219A true KR960009219A (en) 1996-03-22
KR0140635B1 KR0140635B1 (en) 1998-06-01

Family

ID=19391141

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940021064A KR0140635B1 (en) 1994-08-25 1994-08-25 Thin film transistor

Country Status (1)

Country Link
KR (1) KR0140635B1 (en)

Also Published As

Publication number Publication date
KR0140635B1 (en) 1998-06-01

Similar Documents

Publication Publication Date Title
TW283263B (en) Fabrication method of semiconductor device and field effect transistor
KR940001427A (en) Thin film semiconductor device and its manufacturing method
KR930005257A (en) Thin film field effect element and its manufacturing method
KR840008537A (en) Semiconductor device
KR960012564A (en) Thin film transistor and method of forming the same
KR910003838A (en) Thin Film Field Effect Transistors and Manufacturing Method Thereof
KR940010384A (en) Method of manufacturing thin film transistor
KR960009219A (en) Method of manufacturing thin film transistor
KR970054431A (en) MOS transistor and manufacturing method thereof
KR910001876A (en) Semiconductor device manufacturing method
KR970054470A (en) DRAM cell transistor and its manufacturing method
KR940012653A (en) Method of manufacturing thin film transistor
KR950012645A (en) Method of manufacturing thin film transistor of semiconductor device
KR950021749A (en) Semiconductor device manufacturing method
KR970018704A (en) Semiconductor device having MOS transistor of vertical structure and manufacturing method thereof
KR970053596A (en) Thin film transistor and its manufacturing method
KR950030384A (en) Thin film transistor structure
KR920017189A (en) Manufacturing Method of Vertical Channel SOI Device
KR970030794A (en) CMOS transistor and manufacturing method thereof
KR970018717A (en) Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof
KR940003084A (en) MOSFET Structure and Manufacturing Method
KR930015081A (en) Shallow Bonded MOSFET Manufacturing Method
KR970054509A (en) Method of manufacturing thin film transistor
KR970054522A (en) Thin film transistor and method of manufacturing the same
KR950025929A (en) Transistor Manufacturing Method

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060220

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee