KR960008680B1 - Receiving processor and its method in the atm transmission sub-layer and physical layer - Google Patents

Receiving processor and its method in the atm transmission sub-layer and physical layer Download PDF

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Publication number
KR960008680B1
KR960008680B1 KR93028935A KR930028935A KR960008680B1 KR 960008680 B1 KR960008680 B1 KR 960008680B1 KR 93028935 A KR93028935 A KR 93028935A KR 930028935 A KR930028935 A KR 930028935A KR 960008680 B1 KR960008680 B1 KR 960008680B1
Authority
KR
South Korea
Prior art keywords
information
bit register
cell
register
board
Prior art date
Application number
KR93028935A
Other languages
Korean (ko)
Other versions
KR950022437A (en
Inventor
Sung-Ho Jung
Jang-Kyung Kim
Original Assignee
Korea Electronics Telecomm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Korea Electronics Telecomm filed Critical Korea Electronics Telecomm
Priority to KR93028935A priority Critical patent/KR960008680B1/en
Publication of KR950022437A publication Critical patent/KR950022437A/en
Application granted granted Critical
Publication of KR960008680B1 publication Critical patent/KR960008680B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5663—Support of N-ISDN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5684—Characteristics of traffic flows

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

an optical data link (ODL) (1) which receives the cell data from ATM network as optical signal and transforms it to the electrical serial signal; a decoding board (Am7969) (2) which decodes the serial information received from ODL (1) to the electrical signal in the unit of byte; a first 8 bit register (4) which stores the transmission line control information outputted from the decoding board (2) temporarily; a second 8 bit register (3) which stores the 8 bits cell information outputted from the decoding board (2) temporarily; a head error verification board (parallel meggit decoder)(5) which verifies the efficiency of the cell received from the second 8 bit register (3); a cell information store (6) which comprises the two memory bank to store the cell information; a multiplexer (MUX) (7) which multiplexes and processes the cell information of the register (6); the third 8 bit register (8) which stores the multiplexed information temporarily; a register (9) which comprises the 4 FIFO banks to store the information from the third 8 bit register (8); a receiving control board (10) which controls the system.
KR93028935A 1993-12-21 1993-12-21 Receiving processor and its method in the atm transmission sub-layer and physical layer KR960008680B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR93028935A KR960008680B1 (en) 1993-12-21 1993-12-21 Receiving processor and its method in the atm transmission sub-layer and physical layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR93028935A KR960008680B1 (en) 1993-12-21 1993-12-21 Receiving processor and its method in the atm transmission sub-layer and physical layer

Publications (2)

Publication Number Publication Date
KR950022437A KR950022437A (en) 1995-07-28
KR960008680B1 true KR960008680B1 (en) 1996-06-28

Family

ID=19372025

Family Applications (1)

Application Number Title Priority Date Filing Date
KR93028935A KR960008680B1 (en) 1993-12-21 1993-12-21 Receiving processor and its method in the atm transmission sub-layer and physical layer

Country Status (1)

Country Link
KR (1) KR960008680B1 (en)

Also Published As

Publication number Publication date
KR950022437A (en) 1995-07-28

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