KR960008249Y1 - Circuit for power-saving - Google Patents

Abstract

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Description

Power Consumption Reduction Circuit

1 is a block diagram showing a conventional power saving circuit.

2 is a circuit diagram of power consumption reduction according to the present invention.

* Explanation of symbols for main parts of the drawings

R1 to R22: resistors C1 to C4: capacitors

Q1 to Q8: transistor FET: field effect transistor

D1 to D7: Diode ZD1: Zener Diode

PC1: Photo Coupler SCR

The present invention relates to a power saving circuit, and more particularly, a power consumption that directly reduces the power consumption by controlling a driving pulse of a primary switching element in a power-off mode in which horizontal and vertical synchronization signals are not input. Relates to a saving circuit.

With the recent emergence of energy-saving systems for the purpose of environmental protection, power-saving monitors, which are called green monitors, have emerged in the display device world-wide, and various types such as VESA (Video Electric Standards Association) and EPA (Envelopment Protection Agency) Related standards have been enacted and applied.

At this time, power saving adopts a method of shutting down part or all of the power circuit of the display device through a separate signal during a time when the user does not use the system.

That is, if a consumer is using a computer and does not input a key on the keyboard for a predetermined time, the main body of the computer does not output the horizontal sync signal to the monitor. This is called a standby mode and the video signal is turned off. The video is not displayed on the monitor.

If the key is not pressed again for a predetermined time, the vertical synchronization signal is turned off and not output to the monitor. This is called a suspend mode and the power consumption is within 30%.

If the key is not pressed again for a predetermined time, both horizontal and vertical sync signals are turned off and not output to the monitor. This is called a power-off mode and the power consumption is set to 5W or less.

FIG. 1 is a block diagram showing such a conventional power consumption reduction circuit. In the display power management signal generation unit (DPMS), the unit 12 checks the synchronization signal (Sync) of the display device to be normal. Mode, standby mode, suspend mode, power off mode is determined and the corresponding signal is output.

The signal processing unit 13 is connected to the power off mode line of the DPMS unit 12 so that when the output of the DPMS unit 12 indicates the power off mode, the specific B + line on the secondary side is completely blocked to lower the power consumption to 5 W or less. To the photo coupler PC1 through the feedback unit 15.

At this time, since there is no current fed back, the transistor is in an insulated state from the transistor of the photo coupler PC1. Therefore, since the driving pulse of the primary side switching unit 17 is erased, the switching of the transformer is stopped and power consumption is reduced.

At this time, the return signal generation unit 11 detects an input synchronization signal when the user presses a predetermined key to use the monitor. When the synchronization signal Sync is detected, the return signal generator 11 conducts the diode of the photo coupler PC1. Therefore, the current flowing through the diode operates the transistor so that the primary side switching unit 17 operates normally. Since the transformer is switched by the on / off of the switching unit 17 it is possible to output the voltage required for the load.

In addition, the transient state signal processor 14 checks transient states such as moments of power switch-on, moments of power-off mode, and moments of return to perform appropriate processing on the signal processor 13 so that the primary side does not operate at the moment of transients. do.

However, the first diagram described above increases the cost because a high thyristor (also referred to as a thyristor or silicon control rectifier (SCR)) must be used to block the secondary side specific B + line, and at the same time, Since the transient state such as power off mode operation time, return moment, etc. must be properly handled, an additional circuit such as a transient state signal processing unit is required and the circuit becomes complicated.

The present invention is to solve the above problems, and an object of the present invention is to switch to the primary side when a power off mode is entered in a ringing choke converter (RCC) type power circuit in which current loops on an input side and an output side alternately occur. By directly controlling the driving pulse of the device, it is possible to provide a power consumption reduction circuit that can easily and reliably reduce power consumption in the power-off mode.

A feature of the power consumption reduction circuit according to the present invention for achieving the above object is a first switching means which is turned off in a power off code to which a horizontal and vertical synchronization signal is not input, and on when the first switching means is turned off. A second switching means, a photo coupler for turning on the light receiver by the light when the second switching means is turned on, and stopping the switching of the switching transistor by a control signal when the light receiver of the photo coupler is turned on. It consists of a signal processing means.

Hereinafter, a preferred embodiment of a power consumption reduction circuit according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of power consumption reduction according to the present invention. The horizontal and vertical synchronization signal stages (H-Sync and V-Sync) and transistors (Q1 and Q2) become low when the power-off mode is turned on and high when the power-off mode is turned on. The divided resistors R1, R2, R3, and R4 for dividing the power supply 12V which are commonly connected to the horizontal and vertical synchronization signal terminals H-Sync and V-Sync are connected between the bears stages of the terminals.

In addition, a diode D1 is connected to an emitter terminal of the transistor Q1 through a resistor R5, and a diode D2 is connected to an emitter terminal of the transistor Q2 through a resistor R6. The base terminal of the transistor Q3 is connected to the contacts of D1 and D2 through a resistor R7 and a capacitor C1.

The power supply 12V is connected to the base terminal of the transistor Q4, in which the emitter terminal of the transistor Q3 is connected to the collector terminal, through the resistor R8 and the zener diode ZD1.

On the other hand, the power supply 12V is connected to the collector terminal of the transistor Q3 through the resistor R9, and at the same time, the base terminal of the transistor Q5 is connected through the resistor R10. The cathode of the photodiode of the photocoupler PC1 is connected to the collector of the transistor Q5, and the diodes D3, D4, D5 and resistors R12, R13, and R15 are connected to the anode of the photodiode. The power supply terminal 5V, the horizontal synchronizing signal terminal (H-Sync), and the vertical synchronizing signal terminal (V-Sync) are connected to each other.

In addition, a driving voltage B + is connected to the collector terminal of the photo transistor of the photo coupler PC1, and the base of the transistor Q6 is connected to the emitter terminal through a resistor R16 and a capacitor C3 in parallel with the resistor R11. The stages are connected.

In addition, the collector terminal of the transistor Q7 is connected between the resistor R16 and the capacitor C3, and the anode terminal of the thyristor SCR is connected to the base terminal of the transistor Q7 through resistors R21 and R22 connected in parallel. Is connected.

In addition, a resistor R15 and a capacitor C2 are connected in series to the emitter terminal of the photo transistor of the photo coupler PC1, and the thyristor is connected between the resistor R15 and the capacitor C2 through a diode D6. The gate end of the (SCR) is connected.

Meanwhile, a driving voltage B + is connected to a collector terminal of the transistor Q6 through a resistor R17, and a base terminal of the transistor Q8 and an anode terminal of the thyristor SCR are connected in common through a resistor R20. do.

The diode D7 is connected between the emitter terminal of the transistor Q8 and the ground, and the gate terminal of the field effect transistor FET is connected to the collector terminal and the driving voltage B + through the resistor R18. ) Is connected.

In addition, a driving voltage B + is connected to the drain terminal of the field effect transistor FET through a resistor R19 and a driving input terminal D-IN for switching the primary side in parallel.

This design, which is configured as described above, is divided into the normal operation mode, the power-off mode, and the return mode after power-on.

As soon as the power is turned on, starting power is applied from the driving voltage terminal B + to the driving input terminal D-IN of the field effect transistor FET, which is a switching element, through the resistor R19 to start switching at the primary side of the transformer. .

At this time, the thyristor SCR maintains the off state because there is no bias at the gate of the power-on moment. When the thyristor SCR is turned off, the transistor Q7 is turned on and when the transistor Q7 is turned on, the transistor Q6 is turned off. In addition, when the thyristor SCR and the transistor Q6 are turned off, the transistor Q8 is turned on. When the transistor Q8 is turned on, the field effect transistor FET is turned off, so the primary circuit performs a switching operation normally.

At this time, since the horizontal and vertical synchronization signals H-Sync and V-Sync are normally input, 12V is divided by the resistors R1 to R4 and applied to the bases of the transistors Q1 and Q2 to supply the transistors Q1 and Q2. Turn on When the transistors Q1 and Q2 are turned on, the emitter currents of the transistors Q1 and Q2 are applied to the base of the transistor Q3 through the diodes D1 and D2 so that the transistor Q3 is also turned on. On the other hand, since 12V is applied to the base of the transistor Q4 through the zener diode ZD1, it is always turned on before entering the power-off mode.

Therefore, 12V applied to the collector of the transistor Q3 through the resistor R9 is bypassed through the transistor Q4.

Therefore, when the transistor Q3 is turned on, the transistor Q5 is turned off, and the photodiode and the phototransistor of the photo coupler PC1 maintain insulation.

Since the horizontal and vertical synchronization signals (H-Sync and V-Sync) are normally input even after the power is turned on, 12V is divided by the resistors R1 to R4 and applied to the bases of the transistors Q1 and Q2 so that the transistor ( Turn on Q1 and Q2). When the transistors Q1 and Q2 are turned on, emitter currents of the transistors Q1 and Q2 are applied to the base of the transistor Q3 through the diodes D1 and D2 and thus turned on to the transistor Q3.

On the other hand, since 12V is applied to the base of the transistor Q4 through the zener diode ZD1, it is always turned on before entering the power-off mode.

Therefore, 12V applied to the collector of the transistor Q3 through the resistor R9 is bypassed through the transistor Q4.

Accordingly, when the transistor Q3 is turned on, the transistor Q5 is turned off, so that both ends of the port diode of the photo coupler PC1 are reverse biased by 5V and 12V so that the photo coupler PC1 is maintained in the off state. .

Therefore, the transistors Q7 and Q8 are turned on and the transistors Q6 and thyristor SCR are turned off as at the instant of power-on described above, and the primary side normally switches.

In the power-off mode, since the horizontal sync signal H-Sync and the vertical sync signal V-Sync are turned off to be in a low state, the transistors Q1 and Q2 are turned off.

When the transistors Q1 and Q2 are turned off, the transistor Q3 is also turned off. At this time, since 12V is turned off in the off mode, transistor Q4 is also turned off and transistor Q5 is turned on.

Therefore, when the transistor Q5 is turned on, the cathode of the photodiode of the photo coupler PC1 is turned low to conduct the photodiode.

When the photodiode is turned on, current flows through the phototransistor of the photo coupler PC1, and a high voltage is applied to the emitter of the phototransistor. At this time, the high voltage applied to the emitter of the photo transistor of the photo coupler PC1 charges the capacitor C2 and applies a bias to the gate of the thyristor SCR through the diode D6 to turn on the thyristor SCR. Let's do it.

At this time, since the transistor Q7 is kept on, the high voltage of the photo transistor of the photo coupler PC1 is bypassed through the transistor Q7 before the capacitor C3 is charged and the transistor Q6 is turned off. do.

In addition, since the thyristor SCR is turned on and the transistor Q6 is turned off, the driving voltage B + is bypassed through the thyristor SCR, and a low current is applied to the base of the transistor Q8 so that the transistor Q8 is turned on. Turn off. When the transistor Q8 is turned off, a driving voltage B + is applied to a gate of the field effect transistor PET through a resistor R18, so a channel is formed between the drain and the source of the field effect transistor PET. The driving pulse applied to the driving input terminal D-IN through the resistor R19 is bypassed to the source of the field effect transistor PET.

Accordingly, the field effect transistor PET stops switching because no driving pulse is provided to the field input transistor D-IN. Thus, the monitor operates in the power off mode, so power consumption is reduced to 5W or less.

When the return signal is applied, the horizontal and synchronization signals (H-Sync) and the vertical synchronization signals (V-Sync) are normally input, so 12V is divided by the resistors R1 to R4 and applied to the bases of the transistors Q1 and Q2. The transistors Q1 and Q2 are turned on. When the transistors Q1 and Q2 are non-on, the emitter currents of the transistors Q1 and Q2 are applied to the base of the transistor Q3 through the diodes D1 and D2, so that the transistor Q3 is also turned on.

Meanwhile, since 12V is applied to the base of the transistor Q4 through the zener diode ZD1 and the transistor Q4 is also turned on, the 12-valent transistor Q4 applied through the resistor R9 to the collector of the transistor Q3. Bypassed.

At this time, the photodiode of the photo coupler PC1 is turned on by the horizontal and vertical synchronization signals H-Sync and V-Sync provided to the photo coupler PC1 to turn on the photo transistor.

Accordingly, a high voltage is applied to the emitter of the photo transistor of the photo coupler PC1, which turns on the transistor Q6 by charging the capacitor C3 through the resistor R16.

That is, since the capacitance of the capacitor C3 is designed to be smaller than that of the capacitor C2, when the photo coupler PC1 is operated and the transistor Q7 is in the turn-off state, the capacitor C3 is faster than the capacitor C2. The transistor Q6 is turned on by charging the high voltage of the photo transistor.

At this time, since the capacitor C3 is charged with a voltage enough to turn on the transistor Q6, the transistor Q6 is turned on and then turned off immediately. At this time, when the transistor Q6 is turned on, the thyristor SCR is turned off again from the turned on state, and the anode of the thyristor SCR maintains the high state.

Then, when the transistor Q6 is turned off, the high voltage applied to the anode of the thyristor SCR turns on the transistor Q8.

Therefore, when the transistor Q8 is turned on, the field effect transistor FET is turned off, so that a driving pulse bypassed through the field effect transistor PET is driven by the driving input terminal D-IN of the field effect transistor FET. Is applied to initiate normal switching.

As described above, according to the power consumption reduction circuit according to the present invention, when the power-off mode is entered, by directly controlling the driving pulse of the primary switching element without controlling the switching of the primary switching element by the feedback of the secondary side, There is no need for an additional circuit such as a status signal processor, which simplifies the circuit and reduces the cost by eliminating the need for a high thyristor, thereby reducing power consumption in the power-off mode.

Claims (2)

A first switching means which is turned off in a power-off mode in which neither a horizontal nor a vertical synchronization signal is input, a second switching means which is turned on when the first switching means is turned off, and a light emitting part when the second switching means is turned on, And a photo coupler for turning on the light receiver by the light, and signal processing means for stopping the switching of the switching transistor by a control signal when the light receiver of the photo coupler is turned on. The thyristor of claim 1, wherein the signal processing unit comprises a thyristor which is turned on when the light receiving unit of the photocoupler is turned on, and a high voltage of the light receiving unit of the photocoupler when the power-off mode is turned on by the thyristor in the normal mode. And a switching unit configured to bypass the switching circuit and a transistor configured to stop switching by bypassing a driving voltage by turning on a switching transistor when the thyristor is turned on and the switching unit is turned off.