KR960007677B1 - Atm cell boundary identification unit using 5byte syndrom generator - Google Patents

Abstract

The device for discriminating synchronous transfer mode cell boundary using a 5-byte syndrome generator includes: a HEC (Header Error Control) decoding means 10 for generating the syndrome for successive 5 byte data from byte data streams based on a syndrome load signal and a syndrome reset signal and an external input data, extracting the cell boundary, and correcting a single bit error in the cell header; an HEC state tracing means 30 for checking whether a mode set signal provided from the HEC decoding means 10 is in a tracing state, a semi-synchronous state, or a synchronous state; and an HEC driving means 20, for providing the syndrome load signal and the syndrome reset signal, providing the mode signal to the HEC state tracing means 30 and having a plurality of bits error detection, the HEC mode detection, an effective cell transferring functions.

Description

Asynchronous Transfer Mode Cell Boundary Identification Device Using 5-Byte Syndrome Generator

1 is a process flow diagram for a method for extracting cell boundaries according to the prior art;

2 is a flowchart illustrating a method of extracting a cell boundary while moving in byte units according to the prior art;

3 is a schematic functional block diagram for cell boundary extraction according to the present invention;

4 is a functional block diagram of a HEC decoder unit according to the present invention;

5 is a functional block diagram of a HEC driving unit according to the present invention;

FIG. 6 is a timing diagram of the HEC driver of FIG. 3 when there are no errors in headers of two consecutive cells in a tracking state.

7 is a signal generation flowchart of the MODE_SET signal among the output signals of the HEC driver;

8 is a signal generation flowchart of a 53-degree counter reset signal CNT53_RES, a syndrome load signal SYND_LOAD, a syndrome reset signal SYND_RES signal,

9 is a flow chart of the rest of the signal generation of the HEC driver;

10 is a detailed functional block diagram of an HEC state tracking unit;

11 is a state transition diagram of a state tracking unit;

12 is an operation flowchart of a delta counter,

13 is an operation flowchart of an alpha counter,

14 is a diagram illustrating an internal structure of a 5-byte syndrome generator according to the present invention.

* Explanation of symbols for the main parts of the drawings

10 HEC decoder 11: 6 byte shift register

12: 5-byte syndrome generator 13: multiplexer

14: syndrome register 15: XOR operation unit

16: error corrector 17: syndrome pattern decoder

18: syndrome decoder 19: single bit error decoder

20: HEC drive unit 30: HEC state tracking unit

The present invention uses a 5-byte syndrome generator to perform cell boundary identification, which is a core function of the AMT physical layer function, which supports the asynchronous delivery mode (hereinafter referred to as AMT) protocol. Mode (AMT) cell boundary identification apparatus.

Conventional cell boundary identification methods include a method of extracting cell boundaries while moving in units of cells in a tracking state and a method of extracting cell boundaries while moving in units of bytes.

Referring to FIG. 1, which is a flowchart illustrating a method of extracting cell boundaries while moving in units of cells in a tracking state of the related art, 5 bytes of data are inputted from a point assumed to be a header of a cell in a tracking state. If the byte is configured, the head error control (Header Control) (HEC) is verified for the corresponding 5 bytes, and if there is no error in the assumed cell header, the state is shifted to the quasi-synchronous state. In this case, a new cell header is assumed after 1 byte beyond the assumed cell boundary, and the above process is repeated to find the cell boundary. The hardware logic to implement this is simple, but the cell boundary extraction is an error in the transmitted data. Suppose there is no hardware boundary, because the cell boundary is extracted after up to 2754 bytes of data has passed, but the hardware logic is simple, but cell boundary Poor extraction performance

FIG. 2 is a flowchart illustrating a method of extracting cell boundaries while moving in byte units according to the prior art. A hypothetical cell is configured after receiving 1 byte of data in a trace state and constructing 5 bytes of a virtual cell header. If there is no error in the header, it goes to the quasi-synchronous state.If there is an error in the header, it extracts the boundary of the cell by repeating a series of processes of re-validating the HEC by receiving a new byte of data. Since cell boundary extraction is performed around the error detection function block, assuming that there is no error in the transmitted data, it is possible to extract the cell boundary after up to 52 bytes of data has passed. It may be said to be excellent, but hardware logic has the disadvantage of becoming complicated.

The present invention devised to solve the above problems is to provide an asynchronous transfer mode (AMT) cell boundary identification device applied to various devices constituting a broadband integrated information communication network and minimized the hardware burden.

In order to achieve the above object, the present invention receives the data input from the outside, the syndrome load signal and the syndrome reset signal received from the cell boundary while always generating a syndrome for the continuous 5-byte data from the data flow in the unit of byte HEC decoding means for extracting and correcting a single bit error occurring in the cell header, receiving a syndrome signal and a single bit error signal from the HEC decoding means and receiving a modeset signal inputted to the cell boundary extraction state in tracking state and quasi-synchronous state. A HEC state tracking means for determining whether a synchronization state is received, a syndrome and a single bit error signal are received from the HEC decoding means, a syndrome load and a syndrome reset signal are provided, and a mode set signal is provided to the HEC state tracking means and state tracking is performed. Multi-bit error detection under signal Function, characterized in that it includes drive means for the HEC HEC provides a mode detection function and the effective cell forwarding.

Hereinafter, the present invention will be described in detail with reference to FIG. 3.

3 is a schematic functional block diagram for cell boundary extraction according to the present invention, in which 10 is an HEC decoder, 20 is an HEC driver, and 30 is an HEC state tracking unit. As shown in the figure, the HEC decoder unit 10 provides a function of receiving a control signal and extracting a cell boundary from a data flow in bytes and correcting a single bit error occurring in the cell header. D [7: 0] represents the input byte data, Q [7: 0} represents the byte output, and SYND signal indicates the result of HEC verification internally. If there is an error in the cell header, it is outputted as 1. The S_ERR signal is a signal generated to transmit the HE_ driver 20 to the HEC driver 20 when an error occurring in the cell header is a single bit error.

The HEC state tracking unit 30 receives a proper control signal from the HEC decoder unit 10 and the HEC driver 20 described later, and provides a function of determining whether the cell boundary extraction state is a tracking state, a quasi-synchronous state, or a synchronization state. The CS [1: 0] signal is output as 0 when the cell boundary extraction state is in the tracking state, 1 when in the quasi-synchronous state, and 10 when in the synchronous state.

The HEC driver 20 receives a proper signal in addition to a function of controlling the HEC state tracking unit 30 and the HEC decoder 10 to properly drive a multi-bit error detection function, an HEC mode detection function, and an effective signal. Cell forwarding functions and the like.

The single bit error (SINGIE_ERR) signal indicates that the error in the cell header is a single bit error. The multi-bit error (MULTI_ERR) signal indicates that the error in the cell header is a multi-bit error. , D_MODE signals are output as 1 when the HEC mode is the detection mode. The correction mode corrects an error occurring in a cell header when it is a single bit error, and detects when an error occurs in a cell header. The detection mode is a HEC mode that detects only an error when a cell error occurs.

A syndrome load (synd_Lode) signal is a signal generated to transfer a syndrome generated from the 5-byte syndrome generator 12 to a syndrome register 14 in the HEC decoder unit 10, and a Synd_Res signal is a HEC decoder unit ( A signal generated to initialize the contents of the syndrome register 14 in 10). The Mode_Set signal is a signal generated to set the cell boundary extraction state of the HEC state tracker 30.

4 is a block diagram of a HEC decoder according to an embodiment of the present invention, in which 11 is a 6-byte shift register, 12 is a 5-byte syndrome generator, 13 is a multiplexer, 14 is a syndrome register, 15 is an XOR operator, and 16 is an error number. Periodically, 17 represents a syndrome pattern decoder, 18 represents a syndrome decoder, and 19 represents a single bit error decoder.

As shown in the figure, the HEC decoder transmits a signal RQ [7: 0] which is simply delayed by a time for detecting a syndrome pattern through HEC checking by inputting signal D [7: 0] to generate a single signal generated in the cell header. A six-byte shift register 11 that allows bit errors to be corrected, followed by SA [7: 0], which is a syndrome signal corresponding to five consecutive bytes from D [7: 0], which is a series of incoming data streams. A 5-byte syndrome generator 12 that provides a function for generating a clock, and a 16x8 multiplexer that delivers an SA [7: 0] signal when the syndrome_load signal is 1 and an SB [7: 0] signal when 0. (13), a syndrome register 14 storing a signal received through the multiplexer 13, and S [7: 0] which is a syndrome signal transmitted from the syndrome register 14 are updated and output SB [7] XOR operator 15 responsible for generating: 0], generating the 5-byte syndrome The syndrome decoder 18, which transmits the SYND value to 0 only when the syndrome values of the 5-byte syndrome generator are all 0, is set to 1, otherwise, the data corresponding to the cell header is 6 bytes. While transmitting through the shift register 11, 8 syndrome patterns in the case of a single bit error of the first byte among the 5 bytes of data sequentially transmitted are decoded, and the corresponding resultant signal E [7: 0] is transferred to the single signal. A syndrome pattern decoder 17 for correcting a bit error, an error corrector 16 receiving the error correction signal through the syndrome pattern decoder 17, correcting the error, and delivering Q [7: 0], and the syndrome pattern When the error signal through the decoder 17 is a single bit error, it consists of a single bit error decoder 19 that sets the single bit error signal S_ERR to '1'.

Referring to the operation of the configuration, when the cell boundary extraction state is not the tracking state, the 5-byte syndrome generator 12 calculates the syndrome decomposed in the cell header and transfers it to the syndrome register 14, and the transmitted syndrome signal is 4 bytes. The syndrome is updated over the clock via a syndrome update period.

Looking closely at the syndrome characteristic that the 5-byte syndrome generator 12 passes to the syndrome register 14, the corresponding 5 bytes of cell headers are incorrect in all cases where a single bit error occurs in the data, i.e. 40 cases. I can see the fact. Decoding all these patterns and correcting the error can cause a significant amount of decoding logic to solve this problem by updating the syndrome.

The process of correcting single bit error through syndrome update is as follows.

This is the same as the syndrome is calculated for the corresponding 5 bytes of data by adding a byte data assumed to be zero every byte clock period during the syndrome update period. In addition, it takes 6 bytes of clock time to receive the 5 bytes of data assumed to be the cell header and generate the first syndrome vector SA [7: 0] and decode it.

In this regard, the syndrome pattern decoder uses only the syndrome pattern when a single bit error occurs in the first byte of five bytes of data sequentially transmitted while passing the data corresponding to the cell header through the six-byte shift register 11. It can be seen that a single bit error can be corrected by decoding the result signal E [7: 0] corresponding to the decoding result in Eq. In this case, the decoding logic is 5 times simpler. The correlation between the input / output of the XOR operator 15 for syndrome update is as follows.

The correlation between the input / output corresponding to the syndrome decoder 18 for determining the correct and incorrect syndrome calculation is as follows. SYND.D is the input to this register, defined Synd, and the output of this register is SYND.

SYND.D = SA [0] or SA [1] or SA [2] or SA [3] or SA [4] or SA [5] or SA [6] or SA [7]

If the SA [7: 0] signals, which are the syndrome vector signals transmitted from the 5-byte syndrome generator 12, are all zero, the syndrome calculation for the corresponding 5-byte is correct. The correlation between the input / output of the syndrome pattern decoder 17 is as follows. E [7] in the formula indicates that S [7: 0] is set to 1 when the pattern is 10110 as a binary number, and the same relationship applies to E [6] -E [0].

The error corrector 16 provides a function of correcting a single bit error by performing an exclusive OR operation of the RQ [7: 0] signal and the E [7: 0] signal in a one-to-one relationship. Same as

Q [7] = RQ [7] xor E [7], Q [6] xor E [6],. … … … , Q [0] = RQ [0] xor E [0]

When the output of the syndrome pattern decoder 17 is a single bit error, the single bit error decoder 19 is output with the S_err signal set to 1, and the correlation between input and output is as follows.

S_ERR = E [0] or E [1] or E [2] or E [3] or E [4] or E [5] or E [6] or E [7]

In addition to the function of generating a syndrome signal (SYND) through HEC inspection of a portion corresponding to a cell header from a series of data flows D [7: 0], which are supplied with an appropriate control signal from the outside, as described above, If a single bit error occurs, correct it and output Q [7: 0].

5 is a functional block diagram of the HEC driver 20 according to the present invention, in which 21 is a 53-definition counter and 22 is a HEC driver, respectively.

As shown in the figure, the HEC driver 20 is reset when the counter reset (CNT53_RES) signal is 0, and is connected to the 53-definition counter 21 that counts repeatedly from 0 to 52 from the moment when the counter reset (CNT53_RES) signal is 0. Each signal is generated based on the value CNT53 [5: 0], and the HEC is driven by outputting the counter reset signal by receiving the syndrome signal SYND, the single bit error S_ERR, and CS [1: 0]. It consists of an HEC driver 22 for outputting a signal.

FIG. 6 is a timing diagram of the HEC driver 20 of FIG. 3 when there are no errors in headers of two consecutive cells in the tracking state.

In the drawing, H4 and H5 in D [7: 0] represent the fourth byte and the fifth byte of the cell header, respectively, and P1, P2,... Represents cell payload data.

The PS [1: 0] signal is a signal that is not transmitted to the outside of the HEC driver 20 as the output of two registers holding the CS [1: 0] signal when the MODE_SET signal is 1. The SYND_LOAD, MODE_SET, and CNT53_res signals transition from CS [1: 0] to the point where the SYND signal becomes 0 in the trace state, and the 53-definition counter 21 starts to drive. After the quasi-synchronized state, an example of a series of processes in which various other signals are generated based on the 53-definition counter 21 is shown as an example. 7 and 8 illustrate a specific process of generating the signal of the HEC driver 20.

7 is a flowchart illustrating a signal generation of the MODE_SET signal among the output signals of the HEC driver 20. Check if CS [1: 0] is HUNT and PS [1: 0] is HUNT (71). If CS [1: 0] / PS [1: 0] are all HUNT, enter the syndrome value in MODE_SET.D. (75), if any of CS [1: 0] or PS [1: 0] is not HUNT, it is checked whether the count value of the 53-decimal counter 21 is '51' (72). Input '1' to MODE_SET.D (73). If not, enter '0' to MODE_SET.D (74), and then check whether MODE_SET is '1' (76).

As a result of the survey 76, if the MODE_SET value is '1', the value of CS [1: 0] is inputted to PS [1: 0] and returned, and if not, it is returned (77).

To illustrate the flow chart in more detail, CS [1: 0] is a simplified representation of the 2-bit register CS [1: 0] and HUNT means that its value is zero. In the flowchart, PS [1: 0] is a simple representation of the 2-bit register PS [1: 0], and HUNT means that the value is zero. MODE_SET.D represents the input of the register defined as MODE_SET, and the output of the register becomes the MODE_SET signal. As shown in the signal flow diagram, if the state of CS [1: 0] and PS [1: 0] is HUNT indicating the tracking state, the MODE_SET signal becomes the SYND signal. Otherwise, the constant of the 53-decimal counter 21 is fixed. It is generated periodically by decoding the value. In the flowchart, PS [1: 0] ← CS [1: 0] indicates that the value of CS [1: 0] is transmitted to PS [1: 0] when the MODE_SET signal is 1.

8 is a signal generation flowchart of a 53-degree counter reset signal CNT53_RES, a syndrome load signal SYND_LOAD, and a syndrome reset (SYND_RES) signal.

If CS [1: 0] is HUNT and PS [1: 0] is also HUNT (81), if CS [1: 0] / PS [1: 0] are both HUNT, reset the 53-definition counter to ' Set to '0' (90), input the syndrome signal (SYND) signal value to SYND_LOAD.D (91), and then set the SYND_RES value to '1' and return (89). If CS [1: 0] and PS [1: 0] are not HUNT as the result of the investigation (81), the reset value of the 53-degree counter is set to '1' (82) and the 53-degree counter [5: 0] value is' Investigate the 59 'license (83). If the count (83) result is '50', '0' is input to SYND_LOAD.D (85). If '50', '1' is input to SYND_LOAD.D (84). If it is not '5' (86), the process (83) or less is performed again, and if it is '5', the SYND_RES value is set to '0' (87). If the count value is '6', the process returns to step 87. If the count is '6', the SYND_RES value is set to '1' and then returned (88).

More specifically, in the case of CNT53_RES, if the state of CS [1: 0] and PS [1: 0] are all HUNTs indicating the tracking state, CNT53_RES becomes 0 and resets the 53-definition counter 21. It becomes 1 to drive the 53-definition counter 21.

Synd_load.D represents the input of a register defined as SYND_LOAD and the output of that register is SYND_LOAD. As shown in the signal flow chart, when the states of CS [1: 0] and PS [1: 0] are all trace states, the SYND_LOAD signal becomes the SYND signal. Otherwise, the constant value of the 53-degree counter 21 is decoded. Will occur periodically.

9 illustrates a series of processes in which the remaining signals of the HEC driver 20 are generated. Set the value of MODE_SET to '1' (91) and input the value of EFF [0] to EFF [0] .D (92). The SYND value is input to the values of EFF [0] and D (93), and it is checked whether the value of EFF [0] is '1' (94). If the result of the survey 94 is '1', the D_MODE value is output as '1' and the C_MODE value is output as '0' (95). Check if the S_ERR value is '1' (96). If it is not '1', check whether the 53-definition counter value is '4'. Otherwise, return to the process (96). 0 'and multiple error values as' 1' (97,98).

If the result of the survey 94 is not '1', the D_MODE value is '0', the C_MODE value is '1', the single bit error value is '0', and the multiple error value is output as '0' (99). Outputs '1' and returns (103).

If the single bit error value is '1' as a result of the inspection 96, the single bit error value is output as '1' and the multiple error value is output as '0' (100). If the value of EFF [1] is '1' (101), if the value is not '1', the process 103 is performed. If the value is '1', the VC_IND value is outputted as '0' as in the process 98. Then return (102).

In addition to the details, EFF [1: 0] means two register outputs defined as EFF [1: 0]. EFF [0] is set to SYND, the current HEC check syndrome value, and EFF [1] receives the value of EFF [0].

If the value of these two registers EFF [1: 0] is 11, it means that an error has occurred in the header of two consecutive cells. As shown in the signal flow diagram, if the value of EFF [0] is 1, that is, if there is an error in the cell header under HEC checking, the HEC mode is a detection mode, and if the value of EFF [0] is 0, the HEC mode is The correction mode is entered.

And even if there is an error in the cell header, it is not known whether the type of error is a single bit error or a multiple bit error. This can be seen by updating the syndrome and examining the syndrome pattern.

When the value of EFF [0] is 1, the HEC driver 20 examines the S_ERR signal transmitted from the HEC decoder 10 during the syndrome update period to determine that a single bit error has occurred and delivers it to the outside. . If the S_ERR signal does not appear during the syndrome update, a multi-bit error is handled.

As such, the ATM cell boundary identification function module of the present invention is responsible for delivering a valid cell to another function module, and a signal indicating that such a valid cell is transmitted is a VC_IND signal. If there is an error in the cell header that is currently being checked, that is, if EFF [0] is 1 and there is an error in the header of the previous cell, that is, if EFF [0] is 1, an error has occurred in the cell header continuously. The cell under HEC check is treated as an invalid cell unconditionally.

That is, the VC_IND signal is zero. In addition, even if there is no error in the header of the previous cell, the cell is treated as an invalid cell if the type of the error occurring in the current cell header is a multi-bit error.

If there is no error in the cell header, this cell is treated as a valid cell. Even if there is no error in the header of the previous cell and a single bit error occurs in the header of the cell currently being checked, this single bit error is corrected and is being processed as a valid cell. Even when a single bit error occurs in the cell header, the single bit error is corrected and treated as a valid cell. That is, the VC_IND signal is one.

10 is a detailed functional block diagram of the HEC state tracking unit 30, in which 31 is a state tracker (HEC FSM) and 32 is an alpha counter. 33 represents a delta counter, respectively.

A state tracker (hereinafter referred to as HEC FSM) 31 that accepts a SYND_MODE_SET signal to track the HEC state, and an alpha counter that provides an ICC6 signal, which is a signal that identifies the number of six consecutively faulted cells in the cell header ( 32) a delphi counter 33 for providing a VCC5 signal, which is a signal for determining whether the number of continuously error-free cells is five in the cell header.

11 is a state transition diagram of the HEC FSM 31 and operates only when the MODE_SET signal is 1.

The HEC state is passed out of the HEC FSM 31 via C_M [1: 0]. If CS [1: 0] is 0, the HEC state is the tracking state, if 1, the quasi-synchronous state, and if 10, the synchronous state.

If CS [1: 0] is 11, it is undefined and sent to 0 forcibly. In the quasi-synchronous state, that is, in the 1 state, when there are 6 consecutive cells without errors in the cell header, that is, when VCC5 is 1 and the SYND signal is 0, that is, there is no error in the header of the cell under HEC checking, the synchronization state 10 is sent. In the state, if there are 7 consecutive error cells in the cell header, that is, ICC6 is 1 and the SYND signal is 1, that is, if there is an error in the header of this cell during HEC checking, the state goes to tracking state 0.

12 is an operation flowchart of the delta counter 33. Since the delta counter 33 operates only when the CM [1: 0] is 1, i.e., the quasi-synchronous state, it is determined whether the CM [1: 0] is the quasi-synchronous state. If it is not quasi-synchronized (121), the delta [2: 0] value is set to '0' (122). If it is quasi-synchronous, the delta [2: 0] value is set according to whether MODE_SET is '1'. Increment by 1 (124). After the above steps 122 and 124, if the value of the delta counter 32 is 5, the VCC5 signal is set to 1 or '0' and returned (125 to 127).

13 is an operation flowchart of the alpha counter 32. Since the alpha counter 32 operates only when C_M [1: 0] is 10, that is, in a synchronous state, the alpha counter 32 is examined (131). If the state of the alpha counter 32 is set to '0', if the state of the CM [1: 0] is synchronous, depending on whether the value of MODE_SET is '1' (133), the syndrome value is set to '0'. Investigate 1 'authorization (134). If the syndrome value is not '1', the process 132 is performed. If the value is '1', the value of the alpha counter 32 is increased by increasing the value of the alpha counter 32 by '1'. If the value of the alpha counter 32 is 6, the ICC6 signal is set to 1 (137) or is set to '0' (138) and then returned.

14 is a functional block diagram of a 5-byte syndrome generator, in which 41-1 to 44-1 and 45 denote registers, 41-1 to 44-2 denote XOR calculators, 46 masks, and 47 denote XOR calculators.

As shown in the figure, the 5-byte syndrome generator has 8-bit registers 41-1 and RA [7: 0] for receiving an input signal D [7: 0] and outputting RA [7: 0]. The 8-bit register 42-1 which receives the 8-bit signal transmitted through the XOR operator 41-2 and outputs RB [7: 0], and RB [7: 0], performs the XOR operator 43-2. A register 44-1 that receives the 8-bit signal transmitted through and outputs RD [7: 0], and an RD [7: 0] receives the 8-bit signal transmitted via the XOR operator 44-2 and receives RE. A register 45 for outputting [7: 0], and an XOR calculator 41-2, 42-2, 43-2, 44-2 for updating the 8-bit input signal of each of the registers 41-44. A mask 46 for demasking the HEC region during HEC inspection, an output signal from the registers 42-1 to 44-1 of the masked signal MA [7: 0] from the mask 46; (RB [7: 0], RC [7: 0], RD [7: 0] are supplied with the output signal RE [7: 0] from register 45 It consists of an XOR operator 47 that provides the function to find the body syndrome SA [7: 0].

A process of obtaining a syndrome corresponding to five consecutive bytes of data having the above configuration will be described below.

Syndrome generation of five consecutive bytes of data B [1], B [2], B [3], B [4], and B [5] is called Synd [B ₁ B ₂ B ₃ B ₄ B ₅ ]. In this case, it can be seen that the syndrome generation expression is expressed as follows using the principle of superposition.

Synd [B ₁ B ₂ B ₃ B ₄ B ₅ ] = Synd [B ₁ 0] xorSynd [0B ₂ 0]... … … … … xor Synd [0000B ₅ ]

The generalized case to examine the procedure for obtaining each syndrome fragrance is as follows. Synd For [0000B _1], since the order of the data order is below the HEC generator polynomial data that can itself be seen that the syndrome, SynD [000B ₁ 0] and Synd Looking at the relationship between [0000B _1] Synd [000B ₁ 0] is equivalent to syndrome up-update Synd [0000B ₁ ]. Namely, the syndrome of Synd [0000B ₁ ] is changed to S ₀ (t)... S ₇ (t) and Synd [000B ₁ ] syndrome of the correlation between them is as follows. S ₀ (t + T)... S ₇ (t + T), the correlation between them is as follows.

Repeated application of these correlations yields the following equation:

The correlation between the input / output of the XOR calculating sections 41-2 to 44-2 is the same as that of the XOR calculating section 25 in FIG. Output signal RA [7: 0],... RE [7: 0] is respectively Synd [000B ₅ ]... This can be seen by looking at the overall configuration of the 5-byte syndrome generator to indicate Synd [B ₁ 0]. Since the mask 46 is sent by masking the HEC region in a 1010101 pattern from the HEC generation unit (not shown) of the cell header, it is necessary to demask the HEC region when performing the HEC inspection. The correlation between the input / output of the XOR operator 47 is as follows.

As described above, the cell boundary identification function is based on five identical HEC error detection function blocks in the conventional method, but by implementing the function based on the 5-byte syndrome generator in a short time while minimizing the hardware burden compared to the conventional method. It has the advantage of extracting cell boundaries, which can increase the economics and performance of the entire system.

Claims (6)

It extracts cell boundary and receives single bit error in cell header while generating syndrome for continuous 5 byte data from byte data flow. The header error control (hereinafter referred to as HEC) decoding means 10, which receives a syndrome signal and a single bit error signal from the HEC decoding means 10, receives a modeset signal input thereto, and receives a cell boundary. HEC state tracking means 30 for determining whether the extraction state is a tracking state, quasi-synchronous state, and synchronous state, and a syndrome and single bit error signal are input from the HEC decoding means 10 and a syndrome load and a syndrome reset signal are provided. Provide a mode set signal to the HEC state tracking means 30 and provide a state tracking signal CS [1: 0]. And an HEC driving means (20) for providing a multi-bit error detection function, a HEC mode detection function, and an effective cell transfer function. The apparatus of claim 1, wherein the HEC decoding means (10); A six-byte shift register 11 for correcting a single bit zero error occurring in a cell header by simply delaying the input data by the time for detecting the syndrome pattern through HEC checking, corresponding to five consecutive bytes from the input data. A 5-byte syndrome generating means (12) for continuously generating a syndrome signal at every byte clock, connected to the syndrome generating means (12) at 5 bytes, and receiving a syndrome load from the HEC driving means (20) for multiplexing; The syndrome register 14 and the syndrome register 14 which receive a syndrome reset signal from the multiplexer 13 and the HEC driving means 20, receive an output signal of the multiplexer 13, and temporarily store and delay the output signal. Exclusive OR operation means for updating-up the syndrome signal transmitted from the circuit, generating the 5-byte syndrome A syndrome decoder 18 for receiving a syndrome signal from the means 12 and generating a determination signal for syndrome calculation, and an output signal of the syndrome register 14 and receiving data corresponding to a cell header of the six-byte shift register ( 11) A syndrome pattern decoder (17) which decodes eight syndrome patterns and delivers a corresponding result signal to correct a single bit error when a single bit error occurs in the first byte of five bytes of data sequentially transmitted through the same. Error correction means 16 for receiving an output signal from the 6-byte shift register 11 and receiving an error correction signal through the syndrome pattern decoder 17 and correcting the error; Bit error setting the single bit error signal (S_ERR) to '1' when the error signal is a single bit error Coder 19 asynchronous transfer mode cell boundary identification apparatus using a 5-byte syndrome generator comprising the. The method of claim 1, wherein the HEC drive means (20); The 53-definition counter reset signal 21 is repeatedly counted from the moment when the input 53-definition counter reset (CNT53_RES) signal becomes high to 0-52, and the 53-definition counter reset signal is transmitted to the 53-definition counter means 21. And receive the signal SYND from the HEC decoding means 10 and the single bit error signal S_ERR and the 2-bit output signal CS [1: 0] from the HEC state tracking means 30. The HEC driver 22 which is reset according to the 53-definition coefficient (CNT53 [5: 0]) signal from the 53-definition counting means 21, generates each signal based on the output thereof, and outputs an HEC driving signal. An asynchronous transfer mode cell boundary identification device using a 5-byte syndrome generator, characterized in that it comprises a. The method of claim 1, wherein the HEC state tracking means (30); A state tracking unit 31 which receives a syndrome signal SYND from the HEC driving means 20 and a register output MODE_SET signal and outputs a signal CM [1: 0] for tracking the HEC state, and the syndrome The number of cells continuously receiving errors in the cell header by receiving the signal and the register output signal and receiving the output signal CM [1: 0] from the state tracking unit 31. Alpha counting means 32 which provides a signal ICC6 for identifying personality, the register output MODE_SET signal, and an output signal CM [1: 0] from the state tracking unit 31 are received. And a delta counting means (33) for providing a signal (VCC5) for identifying the number of five consecutively error-free cells in the cell header to the state tracking unit (31). Asynchronous Transfer Mode Cell Boundary Identification System. 3. The apparatus according to claim 2, wherein said five-byte syndrome generating means (12); A first resist means 41 for receiving and temporarily storing an input signal D [7: 0] and a second bit for receiving and temporarily storing an 8-bit signal of the first resist means 41 and outputting it; Receiving means 42, the third resist means 43 for receiving and temporarily storing the 8-bit signal of the second resist means 42, and receives the 8-bit signal of the third resist means 43 Fourth resist means 44 for temporarily storing and outputting, fifth resist means 45 for receiving and temporarily storing an 8-bit signal of the fourth resist means 44, and first resist means 41 The demasking means 46 and the output signal demasking signal from the demasking means 46 are received and the output signals from the second to fifth resisting means 42 to 45 are received. Syndrome for each 5 bytes entered And an exclusive OR operation means for obtaining the entire syndromes from the asynchronous transfer mode cell boundary identification device using a 5-byte syndrome generator. 6. The asynchronous transfer mode cell boundary identification device using a 5-byte syndrome generator according to claim 5, wherein said first to fourth resist means (41 to 44) each comprise an 8-bit register and an exclusive OR operation means. .