KR960006345A - Convergence Constant Conversion Circuit for Least Mean Square Equalizers - Google Patents

Convergence Constant Conversion Circuit for Least Mean Square Equalizers Download PDF

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KR960006345A
KR960006345A KR1019940018814A KR19940018814A KR960006345A KR 960006345 A KR960006345 A KR 960006345A KR 1019940018814 A KR1019940018814 A KR 1019940018814A KR 19940018814 A KR19940018814 A KR 19940018814A KR 960006345 A KR960006345 A KR 960006345A
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South Korea
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multiplexer
signal
value
multiplier
count result
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KR1019940018814A
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Korean (ko)
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KR100252339B1 (en
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김영상
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H04L25/025—Channel estimation channel estimation algorithms using least-mean-square [LMS] method
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03592—Adaptation methods
    • H04L2025/03598—Algorithms
    • H04L2025/03611—Iterative algorithms
    • H04L2025/03636—Algorithms using least mean square [LMS]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Abstract

본 수렴상수변환회로는 최소평균자승(LMS) 등화기에 있어서 수렴정도에 따라 수렴정도에 따라 수렴상수를 변환시켜 안정된 수렴을 할 수 있도록 하기 위한 것이다. 이를 위하여 본 회로는 입력신호(X)를 4비트와 6비트 시프트한 값들을 입력신호로 하여 선택적으로 출력하기 위한 제1멀티플렉서; 오차계산값을 8비트 시프트시킨 값과 제1멀티플렉서로부터 출력되는 신호를 승산하기 위한 곱셈기; 곱셈기의 출력신호와 곱셈기의 출력신호를 2비트 시프트한 신호를 선택적으로 출력하기 위한 제2멀티플렉서; 계수갱신방식에 의하여 계수가 갱신될 때마다 발생되는 계수갱신 로드신호를 카운트하기 위한 카운터; 카운터의 카운트 결과값을 디코드하여 제1멀티플렉서의 선택동작을 제어하기 위한 제1디코더; 카운터의 카운트 결과값을 디코드하여 제2멀티플렉서의 선택동작을 제어하기 위한 제2디코더를 포함하도록 구성된다.This convergence constant conversion circuit is designed to achieve stable convergence by converting the convergence constant according to the degree of convergence in the least mean square (LMS) equalizer. To this end, the circuit comprises: a first multiplexer for selectively outputting the values obtained by shifting the input signal X by 4 bits and 6 bits as input signals; A multiplier for multiplying an error calculated value by 8 bits with a signal output from the first multiplexer; A second multiplexer for selectively outputting a signal obtained by shifting the output signal of the multiplier and the output signal of the multiplier by two bits; A counter for counting a coefficient update load signal generated each time the coefficient is updated by the coefficient update method; A first decoder for controlling the selection operation of the first multiplexer by decoding the count result value of the counter; And a second decoder for decoding the count result of the counter to control the selection operation of the second multiplexer.

Description

최소평균자승 등화기에 있어서 수렴상수변환회로Convergence Constant Conversion Circuit for Least Mean Square Equalizers

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 최소평균자승 등화기의 개략도이고,1 is a schematic diagram of a least mean square equalizer,

제2도는 최소평균자승 등화기에 있어서 본 발명에 따른 수렴상수변환회로도.2 is a converging constant conversion circuit diagram according to the present invention in a least mean square equalizer.

Claims (4)

수신된 입력신호(X)를 선형필터링하여 구하여진 출력신호(y)에 대한 오차계산값(e)과 이전의 계수갱신값(W(n)), 상술한 입력신호(X) 및 오차계산값(e)과 수렴상수(μ)를 이용하여 현재의 계수(W(n+1))를 갱신하는 계수갱신방식을 이용하는 최소평균자승 등화기의 수렴상수변환회로에 있어서;The error calculation value e and the previous coefficient update value W (n), the input signal X and the error calculation value for the output signal y obtained by linearly filtering the received input signal X. a convergence constant conversion circuit of a least mean square equalizer using a coefficient update method of updating the current coefficient W (n + 1) by using (e) and a convergence constant μ; 상기 입력신호(X)를 4비트와 6비트 시프트한 값들을 입력신호로 하여 선택적으로 출력하기 위한 제1멀티플렉서;A first multiplexer for selectively outputting 4-bit and 6-bit shifted values of the input signal (X) as input signals; 상기 오차계산값을 8비트 시프트시킨 값과 상기 제1멀티플렉서로 부터 출력되는 신호를 승산하기 위한 곱셈기;A multiplier for multiplying the error calculated value by eight bits and a signal output from the first multiplexer; 상기 곱셈기의 출력신호와 상기 곱셈기의 출력신호를 2비트 시프트한 신호를 선택적으로 출력하기 위한 제2멀티플렉서;A second multiplexer for selectively outputting a signal obtained by shifting the output signal of the multiplier and the output signal of the multiplier by two bits; 상기 계수갱신방식에 의하여 계수가 갱신될 때마다 발생되는 계수갱신로드신호를 카운트하기 위한 카운터;A counter for counting a coefficient update load signal generated each time a coefficient is updated by the coefficient update method; 상기 카운터의 카운트 결과값을 디코드하여 상기 제1멀티플렉서의 선택동작을 제어하기 위한 제1디코더;A first decoder for controlling a selection operation of the first multiplexer by decoding a count result value of the counter; 상기 카운터의 카운트 결과값을 디코드하여 상기 제2멀티플렉서의 선택동작을 제어하기 위한 제2디코더를 포함함을 특징으로 하는 최소평균자승 등화기에 있어서 수렴상수변환회로.And a second decoder for controlling the selection operation of the second multiplexer by decoding the count result value of the counter. 제1항에 있어서,The method of claim 1, 상기 제1디코더는 상기 카운터에서 출력되는 카운트결과값이 제1소정수에 도달하기 전까지는 상기 4비트 시프트한 값이 선택되어 출력되도록 상기 제1멀티플렉서의 선택동작 제어신호를 출력하고, 상기 카운트결과값이 상기 제1소정수에 도달하면 상기 6비트 시프트한 값이 선택되어 출력되도록 상기 제1멀티플렉서의 선택동작 제어신호를 출력함을 특징으로 최소평균자승 등화기에 있어서 수렴상수변환회로.The first decoder outputs a selection operation control signal of the first multiplexer such that the 4-bit shifted value is selected and outputted until the count result value output from the counter reaches the first predetermined number, and the count result is output. And a control signal of a selection operation of the first multiplexer, when the value reaches the first constant, so that the 6-bit shifted value is selected and outputted. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2디코더는상기 카운트결과값이 제2소정수에 도달하기전까지는 상기 곱셈기의 출력신호가 선택되어 출력되도록 제2멀티플렉서의 선택동작 제어신호를 출력하고, 상기 카운트 결과값이 상기 제2소정수에 도달하면 상기 곱셈기의 출력신호를 2비트 시프트한 신호가 선택되어 출력되도록 제2멀티플렉서의 선택동작 제어신호를 출력함을 특징으로 최소평균자승 등화기에 있어서 수렴상수변환회로.The second decoder outputs a selection operation control signal of the second multiplexer so that the output signal of the multiplier is selected and outputted until the count result value reaches a second constant, and the count result value is the second predetermined value. And a control signal of a second multiplexer is selected so that a signal obtained by shifting the output signal of the multiplier by two bits is selected and outputted when the number is reached. The convergence constant conversion circuit of the minimum mean square equalizer. 제3항에 있어서,The method of claim 3, 상기 제1소정수는 상기 제2소정수보다 작은 값을 갖도록 설정됨을 특징으로 최소평균자승 등화기에 있어서 수렴상수변환회로.And the first predetermined constant is set to have a smaller value than the second predetermined constant. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940018814A 1994-07-30 1994-07-30 The convergence constance conversion circuit in the least men square equalizer KR100252339B1 (en)

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KR1019940018814A KR100252339B1 (en) 1994-07-30 1994-07-30 The convergence constance conversion circuit in the least men square equalizer

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KR1019940018814A KR100252339B1 (en) 1994-07-30 1994-07-30 The convergence constance conversion circuit in the least men square equalizer

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100360273B1 (en) * 2000-12-28 2002-11-09 엘지전자 주식회사 Linear compensation adaptive equalizer apparatus and his controll method for digital television repeater
KR100370993B1 (en) * 1998-12-17 2003-02-05 닛뽕덴끼 가부시끼가이샤 Control of amplitude level of baseband signal to be transmitted on the basis of the number of transmission codes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100370993B1 (en) * 1998-12-17 2003-02-05 닛뽕덴끼 가부시끼가이샤 Control of amplitude level of baseband signal to be transmitted on the basis of the number of transmission codes
US7031289B1 (en) 1998-12-17 2006-04-18 Nec Corporation Control of amplitude level of baseband signal to be transmitted on the basis of the number of transmission codes
KR100360273B1 (en) * 2000-12-28 2002-11-09 엘지전자 주식회사 Linear compensation adaptive equalizer apparatus and his controll method for digital television repeater

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