KR960005881A - Bipolar Transistor Manufacturing Method - Google Patents

Bipolar Transistor Manufacturing Method Download PDF

Info

Publication number
KR960005881A
KR960005881A KR1019940017032A KR19940017032A KR960005881A KR 960005881 A KR960005881 A KR 960005881A KR 1019940017032 A KR1019940017032 A KR 1019940017032A KR 19940017032 A KR19940017032 A KR 19940017032A KR 960005881 A KR960005881 A KR 960005881A
Authority
KR
South Korea
Prior art keywords
region
base
emitter
bipolar transistor
forming
Prior art date
Application number
KR1019940017032A
Other languages
Korean (ko)
Other versions
KR0135044B1 (en
Inventor
박현석
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940017032A priority Critical patent/KR0135044B1/en
Publication of KR960005881A publication Critical patent/KR960005881A/en
Application granted granted Critical
Publication of KR0135044B1 publication Critical patent/KR0135044B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

본 발명은 집적도를 개선하며, MOS소자와의 혼용에 효과적인 바이폴라 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a bipolar transistor that improves the degree of integration and is effective for mixing with MOS devices.

본 발명은 바이폴라 트랜지스터의 제조방법에 있어서, 가) 반도체기판의 소정의 부위를 선택적산화공정으로로 형성한 필드산화막으로 활성영역을 정의하는 단계와, 나) 바이폴라 트랜지스터를 형성할 활성영역을 제외한 부분을 제1폴리실리콘 필림으로 마스킹하고 이온주입 한 뒤, 확산하여 콜렉터영역을 형성하는 단계와, 다) 제2질화막으로 에미터영역이 될 부분을 마스킹하고, 산화공정을 실시하여 콜렉터영역 상에 국부적으로 베이스산화막을 성장시킨 후, 제2질화막을 제거하는 단계와, 라) 포토레지스트를 사용하여 베이스영역을 오픈하는 패턴을 만들고 이온을 주입하여 베이스영역을 형성하고, 포토레지스트 패턴을 제거하여, 콜렉터-베이스졍션을 형성하는 단계와, 마) 포토레지스트로 에미터영역을 정의하고, 에미터영역 형성부위에만 이온주입하고 어닐링하여 에미터-베이스졍션과 에미터 영역을 형성하는 단계로 구성한다.According to the present invention, a method of manufacturing a bipolar transistor includes: (a) defining an active region with a field oxide film in which a predetermined portion of a semiconductor substrate is formed by a selective oxidation process; and b) a portion excluding an active region in which a bipolar transistor is to be formed. Is masked with a first polysilicon film and ion implanted, followed by diffusion to form a collector region, c) masking a portion to be an emitter region with a second nitride film, and subjecting it to an oxidation process locally on the collector region. After growing the base oxide film with a second step, removing the second nitride film; d) forming a pattern for opening the base region using photoresist, implanting ions to form a base region, and removing the photoresist pattern, Forming a base cushion; e) defining an emitter region with a photoresist; By mouth, and annealing the emitter-is composed of a base to form a junction with the emitter region.

Description

바이폴라 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 방법에 의한 바이폴라 트랜지스터의 제조공정도이다.2 is a manufacturing process diagram of a bipolar transistor according to the method of the present invention.

Claims (2)

바이폴라 트랜지스터의 제조방법에 있어서, 가) 반도체기판의 소정의 부위를 선택적산화공정으로 형성한 필드산화막으로 활성영역을 정의하는 단계와, 나) 바이폴라 트랜지스터를 형성할 활성영역을 제외한 부분을 제1폴리실리콘 필림으로 마스킹하고 이온주입 한 뒤, 확산하여 콜렉터영역을 형성하는 단계와, 다) 제2질화막으로 에미터영역이 된 부분을 마스킹하고, 산화공정을 실시하여 콜렉터영역 상에 국부적으로 베이스산화막을 성장시킨후, 제2질화막을 제거하는 단계와, 라) 포토레지스트를 사용하여 베이스영역을 오픈하는 패턴을 만들고 이온을 주입하여 베이스영역을 형성하고, 포토레지스트 패턴을 제거하여, 콜렉터-베이스졍션을 형성하는 단계와, 마) 포토레지스트로 에미터영역을 정의하고, 에미터영역 형성 부위에만 이온주입하고 어닐링하여 에미터-베이스졍션과 에미터 영역을 형성하는 단계를 포함하는 것이 특징인 바이폴라 트랜지스터 제조방법.In the method of manufacturing a bipolar transistor, a) defining an active region with a field oxide film formed by forming a predetermined portion of a semiconductor substrate by a selective oxidation process, and b) excluding a portion excluding an active region for forming a bipolar transistor, Masking with silicon film, implanting ions, and diffusing to form a collector region; c) masking a portion of the emitter region with a second nitride film, and subjecting the base oxide film locally on the collector region by performing an oxidation process. After the growth, removing the second nitride film; d) forming a pattern for opening the base region using photoresist, implanting ions to form the base region, and removing the photoresist pattern to remove the collector-base cushion. E) defining an emitter region with photoresist, ion implantation only at the emitter region formation site, and And forming a emitter-base cushion and an emitter region by niling. 제1항에 있어서, 상기 (마)단계에서 제 2 폴리실리콘 막을 형성하고 포토레지스트로 에미터영역을 정의한 후 에미터영역 형성 부위의 제 2 폴리실리콘에만 이온주입하고 어닐링하여 에미터-베이스졍션과 에미터 영역을 형성하는 것이 특징인 바이폴라 트랜지스터 제조방법.2. The method of claim 1, wherein in the step (e), the second polysilicon film is formed, the emitter region is defined by photoresist, and then ion implanted and annealed only to the second polysilicon of the emitter region formation site to emitter-base cushion and A method of manufacturing a bipolar transistor, characterized by forming an emitter region. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940017032A 1994-07-15 1994-07-15 Fabrication method of bjt KR0135044B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940017032A KR0135044B1 (en) 1994-07-15 1994-07-15 Fabrication method of bjt

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940017032A KR0135044B1 (en) 1994-07-15 1994-07-15 Fabrication method of bjt

Publications (2)

Publication Number Publication Date
KR960005881A true KR960005881A (en) 1996-02-23
KR0135044B1 KR0135044B1 (en) 1998-04-20

Family

ID=19388033

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940017032A KR0135044B1 (en) 1994-07-15 1994-07-15 Fabrication method of bjt

Country Status (1)

Country Link
KR (1) KR0135044B1 (en)

Also Published As

Publication number Publication date
KR0135044B1 (en) 1998-04-20

Similar Documents

Publication Publication Date Title
JP3205361B2 (en) Method for manufacturing power MOS transistor with longitudinal current
KR970703616A (en) METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH BICMOS CIRCUIT
KR910013577A (en) Manufacturing Method of Semiconductor Device
JPH01264253A (en) Manufacture of semiconductor device
KR960704346A (en) BIPOLAR TRANSISTOR PROCESS
KR970053884A (en) A method for manufacturing a semiconductor integrated circuit device capable of independently forming a MOS transistor
KR920007200A (en) BiCMOS field effect transistor and its manufacturing method
JP3470155B2 (en) Improved bipolar transistor
JPH04343434A (en) Manufacture of semiconductor device
KR960005881A (en) Bipolar Transistor Manufacturing Method
EP0736898A3 (en) BICMOS device and method for the fabrication thereof
KR970017994A (en) Method for Fabricating Multiple Microelectronic Circuits on SOI
JPH0637266A (en) Mos integrated circuit and manufacture thereof
KR970003939A (en) Method for manufacturing bipolar transistors of horizontal structure
JPH0897231A (en) Manufacture of semiconductor device
JP2953020B2 (en) Method for manufacturing semiconductor device
RU2065225C1 (en) Method of manufacture of bipolar transistor with emitter- coupled gate
JPH04213834A (en) Manufacture of bipolar integrated circuit
JPH01235367A (en) Manufacture of semiconductor device
TW283794B (en) Fabrication method of transistor with vertical bipolar junction
JPH08204041A (en) Manufacture of semiconductor device
JPH08204040A (en) Manufacture of semiconductor device
JPH0656836B2 (en) Method for manufacturing semiconductor device
JPS63104367A (en) Manufacture of semiconductor device
JPH061815B2 (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20041230

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee