KR960005814A - Quantum thin wire fabrication method using GaAs / AlGaAs substrate - Google Patents

Quantum thin wire fabrication method using GaAs / AlGaAs substrate Download PDF

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KR960005814A
KR960005814A KR1019940017508A KR19940017508A KR960005814A KR 960005814 A KR960005814 A KR 960005814A KR 1019940017508 A KR1019940017508 A KR 1019940017508A KR 19940017508 A KR19940017508 A KR 19940017508A KR 960005814 A KR960005814 A KR 960005814A
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South Korea
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substrate
gaas
quantum thin
algaas
groove
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KR1019940017508A
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Korean (ko)
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KR0130610B1 (en
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민석기
김무성
김용
이민석
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김은영
한국과학기술연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

본 발명은 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법에 관한 것으로, 종래의 양자세선 제작방법은 직접 GaAs 기판위에 V홈을 형성하고 그 위에 에피성장(epitaxial growth)을 실시하여 양자세선을 제작하는데, 상기와 같은 종래 양자세선 제작방법은 기판상에 형성되는 V 홈에 의해 에피층의 울퉁불퉁하게 되는 문제점이 있었다. 본 발명은 이러한 문제점을 해결하기 위하여 기판에 AlGaAs를 한층 더 성장시킨후 V홈을 형성함으로써 보다 효과적으로 양자세선을 형성시키고, 확산 제한 용액을 이용하여 마스크없이 양지세선을 보호하면서 윗면 양자우물(top quantum well)을 효과적으로 제거하는 동시에 V홈 형성에 따른 울퉁불퉁한 에피층을 간단하게 평탄화하 수 있도록 하는 GaAs/AlGaAs기판을 이용한 양자세선 제작벙법을 제공하는 것이다.The present invention relates to a quantum thin wire manufacturing method using a GaAs / AlGaAs substrate, the conventional quantum thin wire manufacturing method to form a quantum thin wire by directly forming a V groove on the GaAs substrate and subjected to epitaxial growth thereon, The conventional quantum thin wire manufacturing method as described above has a problem in that the epi layer is uneven due to the V groove formed on the substrate. In order to solve this problem, the present invention further grows AlGaAs on the substrate to form V-grooves to form quantum thin lines more effectively, and protects the fine thin lines without a mask by using a diffusion limiting solution. The present invention provides a method for fabricating a quantum thin line using a GaAs / AlGaAs substrate, which effectively removes wells and easily flattens an uneven epitaxial layer due to V groove formation.

Description

GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법Quantum thin wire fabrication method using GaAs / AlGaAs substrate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 양자세선 제작공정도.1 is a quantum thin wire manufacturing process according to the present invention.

제2도는 본 발명에 따른 양자세선이 제작된 에피층의 단면사진으로, (가)는 에피층 성장 후의 주사전자 현미경(Scanning electron microscope : SEM)단면 사진이고, (나)는 양자세선부분의 투과전자 현미경(Tunneling electron microscope : TEM)사진이며, (다)는 윗면 양자우물을 제거한 주사전자 현미경(Scanning electron microscope : SEM)사진이다.FIG. 2 is a cross-sectional photograph of an epitaxial layer in which a quantum thin line is manufactured according to the present invention. Tunneling electron microscope (TEM) picture, (C) is a scanning electron microscope (SEM) picture with the top quantum well removed.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : GaAs 가판 20,40 : AlGaAs 층10: GaAs substrate 20, 40: AlGaAs layer

30 : 포토레지스트팬턴 50 : GaAs 층.30: photoresist pantone 50: GaAs layer.

Claims (6)

GaAs기판상에 AlGaAs층을 성장시키는 공정과, 상기 AsAlGaAs층 위에 원하는 방향으로 포토레지스트패턴을 형성하는 공정과, 포토공정을 통해 상기 AlGaAs층이 형성된 기판상에 V홈을 형성하는 공정과, 상기 V홈 위에 에피성장하여 양자세선을 형성하는 공정으로 이루어지는 것을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.Growing an AlGaAs layer on a GaAs substrate, forming a photoresist pattern on the AsAlGaAs layer in a desired direction, forming a V groove on a substrate on which the AlGaAs layer is formed through a photo process, and A method for fabricating a quantum thin line using a GaAs / AlGaAs substrate, comprising epitaxial growth on a groove to form a quantum thin line. 제1항에 있어서, 확산제어에칭액으로 윗면 양자우물을 제거하여 양자세선을 평탄화하는 공정을 더 포함하는 것을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.The method of claim 1, further comprising the step of flattening the quantum fine lines by removing the top quantum wells with a diffusion control etchant. 제2항에 있어서 확산제어 에칭액은 H2SO4: H2O2O (30 :1 :1의 부피 비율)이 사용됨을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.3. The method of claim 2, wherein the diffusion control etching solution is H 2 SO 4 : H 2 O 2 O (30: 1: 1 volume ratio). 제1항에 있어서, V홈 형성공정은 기판과 AlGaAs층의 에칭특성각도(C1)가 기판이 파인각도(C2)보다 작게 하여 형성하는 것을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.The quantum thin line fabrication process of claim 1, wherein the V-groove forming process is performed such that the etching characteristic angle (C 1 ) of the substrate and the AlGaAs layer is smaller than the fine angle (C 2 ) of the substrate. Way. 제1항에 있어서, AlGaAs층의 두께는 상기 V홈 형성에 따른 기판의 식각 두께보다 작게 형성하는 것을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.The method of claim 1, wherein the thickness of the AlGaAs layer is smaller than the etching thickness of the substrate according to the V groove formation. 제2항 또는 제3항에 있어서, 확산제어에칭액이 흐르는 방향에 V홈이 직각되게 기판을 위치시키는 것을 특징으로 하는 GaAs/ AlGaAs 기판을 이용한 양자세선 제작방법.The quantum thin line manufacturing method using a GaAs / AlGaAs substrate according to claim 2 or 3, wherein the substrate is positioned so that the V groove is perpendicular to the direction in which the diffusion control etching liquid flows. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940017508A 1994-07-20 1994-07-20 METHOD FOR MAKING QUANTOM FINE-WELL USING GaAs/AIGaAs SUBSTRATE KR0130610B1 (en)

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KR1019940017508A KR0130610B1 (en) 1994-07-20 1994-07-20 METHOD FOR MAKING QUANTOM FINE-WELL USING GaAs/AIGaAs SUBSTRATE

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KR1019940017508A KR0130610B1 (en) 1994-07-20 1994-07-20 METHOD FOR MAKING QUANTOM FINE-WELL USING GaAs/AIGaAs SUBSTRATE

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