KR960004827Y1 - Horizontal sync. stabilizing circuit - Google Patents

Abstract

None.

Description

Horizontal synchronous stabilization circuit

1 is a block diagram of a conventional horizontal synchronization circuit.

FIG. 2 is a detailed circuit diagram of the FIG. 1 FBT part. FIG.

3 is an output waveform diagram of a second diagram terminal HS.

4 is an output waveform diagram of a horizontal synchronous signal generator of FIG.

5 is an explanatory diagram of jitter shapes appearing on an actual screen.

6 is a block diagram of a horizontal synchronous stabilization circuit of the present invention.

7 is a waveform diagram of each point in FIG. 6;

* Explanation of symbols for main parts of the drawings

1: Horizontal drive pulse generator 13: Horizontal output waveform voltage divider

14: FBT unit 15: power supply unit

16: phase detector 17: voltage controlled oscillator

18: distribution unit 19: error detection unit

The present invention relates to a horizontal synchronization stabilization circuit, and in particular, horizontal synchronization that eliminates anomalies such as jitter by stabilizing a horizontal synchronization signal of a moving picture in which contrasts intersect in wireless broadcasting or caption broadcasting. It relates to a stabilization circuit.

In the conventional horizontal synchronization circuit, as shown in FIG. 1, the horizontal drive pulse generator 1 and the horizontal output transistor Q1 which turn on / off the horizontal output transistor Q1 by outputting the horizontal drive pulse signal are turned on / off. When off, the power supply unit 4 supplies power to the FBT unit 3 which induces voltage to the secondary coil Ls, and when the voltage signal is input from the FBT unit 3, the character multiple system. It consists of a horizontal synchronous signal generation part 5 which outputs a horizontal synchronous signal to the part 6.

The operation of the conventional circuit is described in detail with reference to FIG. 1 as follows.

The horizontal output transistor Q1 outputs the horizontal drive pulse signal from the horizontal drive pulse generator 1 is turned on / off. The FBT unit 3, which receives power from the power supply unit 4 to the primary coil Lf, induces a voltage to the secondary coil Ls when the horizontal output transistor Q1 is turned on / off.

The voltage output from the secondary coil Ls of the FBT unit 3 is divided by the resistors R2 and R3 via the protection resistor R1. The voltage divided by the resistors R2 and R3 turns the transistor Q2 on and off. When this transistor Q2 is turned on and off, the collector phase outputs an antiphase waveform of a base input waveform. It is input to the character multiple system unit 6 to operate as a horizontal synchronization signal.

This problem of the conventional circuit will be described with reference to FIGS. 2 to 5 as follows.

The detailed circuit of the FT part 3 is shown in FIG. 2, but when voltage variation occurs in the winding of the high voltage generator 7, voltage fluctuation occurs in the primary feedback winding Lfb, and the voltage amplitude output to the terminal HS is changed. . In the conventional circuit, the voltage output to the terminal HS of the RF part 3 is inputted to the horizontal synchronous signal generator 5 to divide the voltage into the resistors R2 and R3 to form a reference level. The output signal of the waveform-shaped horizontal synchronous signal generator 5 according to the difference of is shown in FIG.

As shown in FIG. 4, there is a problem in that the high voltage is changed and the width of the horizontal synchronization signal is changed.

In addition, as the width of the horizontal synchronization signal becomes wider and narrower, the phenomenon that appears on the actual screen appears as jitter, as shown in FIG. 5. As the high voltage increases and the width of the synchronization signal increases, the synchronization signal with the immediately preceding synchronization signal is increased. In the relationship, the period becomes smaller than 1H, and it is displayed in front on the actual screen, and when the high voltage decreases and the width of the synchronization signal is narrowed, the period becomes larger than 1H in the relationship with the immediately preceding synchronization signal. This occurs and there is a problem that is displayed later.

In view of the problems of the conventional circuit, the present invention applies a horizontal synchronizing signal output from the horizontal force waveform divider and a signal output from the voltage controlled oscillator to the phase detector, and then changes the phase by a phase difference to stabilize the horizontal oscillation frequency. The horizontal synchronous stabilization circuit for outputting the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 6, the horizontal synchronous stabilization circuit of the present invention outputs a horizontal drive pulse signal to turn on / off the horizontal output transistor Q1, and a horizontal output transistor Q1. When turned on / off, the FBT unit 14 for inducing high voltage, the power supply unit 15 for supplying power to the FBT unit 14, and the horizontal output transistor Q1 voltage divider are divided. A horizontal output waveform divider 13, a voltage controlled oscillator 17 oscillating at a unique oscillation frequency, a distribution unit 18 for converting a waveform input from the voltage controlled oscillator 17 into a low frequency signal; A phase detector 16 for controlling the synchronization timing by comparing the phase of the signal input from the distribution unit 18 with the signal input from the horizontal output waveform divider 13, and the phase detector 16. If the signal being compared at is out of phase And an error detector 19 for converting an error current into an error voltage and applying the same to the voltage controlled oscillator 17. The horizontal output waveform divider 13 has a horizontal output transistor Q1 at one end of the capacitor C2. Connected to the collector and the other end is grounded via a capacitor C3, the interconnection point of the capacitors C2 and C3 is configured to be grounded via a resistor R7 and R8, and the phase detector 16 is horizontal When the phases of the signals input from the output waveform divider 13 and the divider 18 are compared and the phases do not match, an error voltage is applied to the voltage controlled oscillator 17 through the error detector 19 to generate an oscillation frequency. And to generate a stable horizontal synchronizing signal.

Effects of the present invention circuit constructed as described above will be described in detail with reference to FIGS. 6 and 7.

The horizontal drive pulse generator 11 turns on / off the horizontal output transistor Q1 that outputs a pulse to drive the FBT unit 14 to which a DC voltage is supplied from the power supply unit 15. At this time, since the horizontal output waveform of 1,000 [Vpp] or more generally occurs in the collector of the horizontal output transistor Q1, it is difficult to use the general resistor to divide the horizontal output waveform.

That is, when the voltage divider capacitors C2 and C3 are connected in series, the horizontal output transistor Q1 collector output waveform is divided into waveforms having a constant amplitude. The waveforms are connected in series to the voltage divider resistors R7 and R8. Dividing to the desired amplitude by using.

The divided waveform is shown in FIG. 7A.

The advantage of this partial pressure method is that the conventional partial pressure method is a method of dividing the waveform generated by feeding back the amount of variation on the high pressure side. When the screen is dark at 27KV and the high voltage rises to 28KV, and the high voltage drops to about 26KV) When the voltage divider of the desired amplitude is made, about 1.0% of variation occurs, whereas the voltage dividing method of the circuit of the present invention is FT part 14. Since the primary winding of is used, the influence from the secondary side is small and the collector residual width of the horizontal output transistor (Q1) is about 1.0 [KVpp].

In this way, when the waveform of FIG. 7a having the desired amplitude is inputted to the phase detector 16 at the position (a), the waveform outputted from the voltage controlled oscillator 17 passes through the distribution unit 18 to the point (c). Phase is compared with the waveform of FIG.

To explain the operation of the phase detector 16, first, the waveform of FIG. 7a is input to the phase detector 16 immediately after the TV, and the voltage controlled oscillator 17 oscillates at a unique oscillation frequency. Oscillation waveforms such as degrees are input to the phase detector 16 via the distribution unit 18.

The phase detector 16 compares the phases of the two input waveforms and inputs the error current to the error detector 19 composed of the resistor R9 and the capacitor C4 to output an error voltage when the phases are different. It is used as a control voltage of the voltage controlled oscillation unit 17.

When the phase difference between the two input waveforms is large, the phase detector 16 inputs a large amount of error current into the error detector 19 to increase the control voltage applied from the error detector 19 to the voltage controlled oscillator 17 to increase the oscillation frequency. Change it.

That is, when the high voltage rises and the horizontal synchronous width becomes large or the high voltage falls and the horizontal synchronous width decreases, the phase detector 16 outputs an error current by the phase difference to speed up the oscillation frequency of the voltage controlled oscillator 17 (in this case, Slows down horizontal synchronization (in this case, slows down horizontally) so that it always has a constant synchronization timing.

When the circuit of the present invention configured as described above is used, the TV screen becomes bright or dark, and the amplitude of the horizontal synchronizing signal is stabilized even when the high voltage is fluctuated, thereby eliminating the jitter phenomenon in which the position of the subtitle is slightly changed and the screen is stabilized.

Claims (3)

A horizontal drive pulse generator 11 for outputting a horizontal drive pulse signal to turn on / off the horizontal output transistor Q1, and an FBT unit for inducing high voltage when the horizontal output transistor Q1 is turned on / off. (14), a power supply unit 15 for supplying power to the FTV unit 14, a horizontal output waveform divider 13 for dividing the collector voltage of the horizontal output transistor Q1, and a unique oscillation A voltage controlled oscillator 17 oscillating at a frequency, a divider 18 for converting a waveform input from the voltage controlled oscillator 17 into a low frequency signal, a signal inputted from the distributor 18 and the Phase current detector 16 for controlling the synchronization timing by comparing the phase of the signal input from the horizontal output waveform divider 13 and error current input when the phase of the signal compared by the phase detector 16 is different Is converted into an error voltage Horizontal synchronization, characterized in that the stabilizing circuit configured as an error detection section (19) for applying a control oscillation unit (17). The horizontal output waveform divider (13) of claim 1, wherein the collector of the horizontal output transistor (Q1) is grounded through the capacitors (C2) and (C3), and the interconnection points of the capacitors (C2) and (C3). The horizontal synchronous stabilization circuit, characterized in that configured to be grounded via a resistor (R7) (R8). The phase detector 16 compares the phases of the signals input from the horizontal output waveform divider 13 and the divider 18 and, if the phases do not match, through the error detector 19. A horizontal synchronous stabilization circuit, characterized in that configured to generate a stable horizontal synchronous signal by varying the oscillation frequency by applying an error voltage to the voltage controlled oscillator 17 as a control voltage.