KR960004716B1 - Atm adaptation layer and atm layer interface control unit - Google Patents

Abstract

The apparatus includes an ALL transmission buffer(12) for storing and sending ATM cell, an ALL transmission controller(13) for sending the transmission clock signal to the transmission buffer(12) and for sending frame signal, clock signal and synchronous signal to an ATM, an ATM reception buffer(14) for receiving signals transmitted from the ALL transmission controller(13), an ALL reception controller(15) for generating the sent request signal, an ATM transmission buffer(19) for storing ATM cell, an ATM transmission controller(18) for sending ATM cell, frame signal, clock signal and synchronous signal to the ALL, and a ALL reception buffer(16) for receiving ATM cell and output control signal transmitted from the ALL reception controller(17).

Description

Matching control device between the Asynchronous Transfer Mode (ATM) adaptation layer and the Asynchronous Transfer mode (ATM) layer

1 is a schematic block diagram of a match control device between an ATM adaptation layer and an ATM layer.

2 is a processing flowchart according to a transmission operation.

3 is a processing flowchart according to a receiving operation.

4 is a timing diagram of a signal according to a transmission / reception operation.

* Explanation of symbols for main parts of the drawings

11: ATM generation block 12: Tx transmit buffer

13: transmit control block 14: Tx receive buffer

15: Receive control block 16: Rx receive buffer

17: Rx receive control block 18: Rx transmit control block

19: Rx transmit buffer 20: ATM cell processing block

The present invention relates to an asynchronous transmission mode (ATM) layered layer (ATM) in a method using ATM, which is a transmission method of a broadband integrated information communication network (hereinafter referred to as B-ISDN) in an international standard organization (TSS). A matching control device according to transmission and reception cell transmission between an ATM Adaptation Layer (hereinafter referred to as AAL) and an Asynchronous Transfer Mode (ATM) layer.

In order to provide type-specific services in B-ISDN, 53 octets of ATM cells are used. The ATM cell is first transformed into a 48 octet ATM adaptation layer-protocol data unit (hereinafter referred to as a PDU), and then combined with a 5-octet ATM header to form a 53 octet ATM cell. Through the processing of the layer is transmitted to the B-ISDN.

Unlike the method of transmission by allocation of time slots at regular intervals used for data transmission in a conventional synchronous network, generation is fixedly or variably in an ATM network. Whenever it is generated by asynchronous transmission and reception between the layers, for example, the configuration of the AAL transceiver for a fixed bit rate service transmission is described in the patent application (application number; 92-24193, 24194) Specified.

An object of the present invention is to support the transmission and reception between all types of AAL and ATM layers, and in particular, for a service that is sensitive to cell delay fluctuations that may occur for a service such as a fixed bit rate, it is directly transmitted in one cell unit without waiting in a buffer. AAL and ATM are designed to enable stable cell transmission between AAL and ATM layer, because it reduces and delays and receives and receives the reception status of the other layer, thus preventing other cell loss due to buffer overflow. It is to provide a matching control device between layers.

In order to achieve the object of the present invention, the present invention, the ALL-side transmission buffer for storing the ATM cell from the ATM cell generating means according to the cell clock, and receives the cell clock and the frame signal output from the ATM cell generating means And all transmission control means for transmitting a transmission clock to the ALL transmission buffer to transmit an ATM cell when receiving the transmission from the ATM layer, and outputting a frame signal, a clock, and a synchronization signal to the ATM, and an ATM from the ALL transmission buffer. An ATM layer receiving buffer receiving a cell, receiving a frame signal and a clock from an ALL transmission control block, and receiving a storage status signal from the ATM layer receiving buffer, and providing a transmission request signal to the ALL transmission control means. An ALL side reception control means for receiving a frame signal and a transmission clock from the ALL side transmission control means and an ALL side; The ALL-side transmit buffer that stores the ATM cell to be transmitted, and when a transmit request signal is received from ALL, the transmission click is transmitted to the ALL-side transmit buffer to transmit the ATM cell, and the frame signal, the clock signal, and the synchronization signal are transmitted. An ATM side transmission control means for transmitting to the ATM side, and a control signal for providing a transmission request signal indicating whether or not reception is possible to the ATM side reception control means, receiving a frame signal, a clock, and a synchronization signal, and outputting a received ATM cell. And an ALL side reception buffer for receiving an ATM cell from the ATM hierarchical side and an output control signal from the ALL side reception control means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a schematic block diagram of the present invention, in which 11 is an ATM generation block, 12 is a Tx transmit buffer, 13 is a Tx transmit control block, 14 is a Tx receive buffer, 15 is a Tx receive control block, and 16 is an Rx receive buffer. 17 denotes an Rx receive control block, 18 denotes an Rx transmit control block, 19 denotes an Rx transmit buffer, and 20 denotes an ATM cell processing block.

As shown in the figure, the configuration of the matching control device between the ALL and the ATM layer is such that the ATM cell supplied from the ATM cell generation block 11 specified in the present invention (Application No. 92-24194) filed by the present applicant is a cell clock (Cell). The cell clock Cell_Clk is supplied to the Tx transmission control block 13 at the same time as stored in the Tx transmission buffer 12 according to -Clk, and it is determined whether 53 ATMet of ATM cells are stored.

Meanwhile, the Tx reception buffer 14 provides the buffer storage state to the Tx reception control block 15, and the Tx reception control block 15 transmits a request signal TCell-Req indicating whether or not reception is possible. 13), the Tx transmission control block 13 determines this and transmits it. At the time of transmission, transmission data (TCell-Dat) from the Tx transmission buffer 12 and synchronization signal (TCell-Sync), frame signal (TCell-Frm) and transmission clock (TCell-Clk) from the Tx transmission control block 13 The signals are transmitted to the Tx transmit buffer 14 and the Tx receive control block 15 according to each signal.

When transmitting from the ATM layer to ALL, the Rx reception buffer 16 notifies the Rx reception control block 17 of the buffer status and the Rx reception control block 17 sends a RCell-Req signal indicating whether or not the reception is possible. The Rx transmission control block 18 transmits the signals of the synchronization signal (RCell-Sync), the frame signal (RCell-Frm), and the clock signal (RCell-Clk) at the same time. The ATM cell, which is a data cell (RCell-Dat), is supplied from the buffer 19 to the Rx reception buffer 16 and the Rx reception control block 17.

The ATM cell processing block 20 receives the notification from the Rx reception control block 17 that the ATM cell has been stored in the Rx reception buffer 16, checks whether the virtual channel is compatible with the ATM header, and checks the ALL header. It checks and restores service data.

The detailed configuration and function of the ATM cell processing block 20 is specified in the earlier application (Application No. 92-24193) filed by the applicant.

2 is a process flow diagram according to the transmission operation in ALL, and the transmission process in ALL is started by the Tx transmission control block 13.

The transmission process starts (31) and initializes the counter to set the counter value to 1 (CNT = '1') 32, and checks whether the cell drive frame is 1 (Cell_Frm = '1') ( 33). If the cell drive frame is not 1, the result is returned. If the cell frame is 1 (Cell_Frm = '1'), the counter is incremented by 1 according to the input data and the cell clock (Cell_Clk) (CNT = CNT + 1) (34).

As a result, the counter value is increased, but when the cell frame is 0, the counter value remains 1 without increasing the counter value.

After determining the counter value and checking whether the value is 53 (octet) (CNT = '53 ') (35), if it is' 53', one ATM cell is generated and stored in the Tx transmission buffer ( 36), it is determined whether the ATM layer can be transmitted according to the TCell-Req signal (36), and the transmission is performed on a cell-by-cell basis (38). (39) returns to the beginning at the same time.

3 is a process flow diagram according to the reception operation in ALL, where the reception process in ALL is started by the Rx transmission control block 13.

The reception process starts (41), and after setting the counter value to 1 in the initialization step 42 (CNT = '1'), it is determined whether to transmit to the AAL layer according to the RCell-Req signal. If the reception is impossible (43), it returns to the initialization step 42 and waits until transmission is possible.

If reception is possible, it is checked whether the cell drive frame is 1 (RCell-Frm = '1') (44), and if it is '1', the counter value is increased according to the input data and the cell clock (RCell-Clk). (45), check whether the counter value is 53 (CNT = '53 ') (46), if it becomes' 53', know that one ATM cell has been received and store it in the Rx reception buffer (47). At the same time, the cell is received (48), the virtual channel for the ATM header, the payload type, the cell priority, and the AAL-PDU are processed to restore and terminate the service data. (49)

4 is a timing diagram of each signal transmitted during transmission and reception.

Details of each signal shown in the figure are as follows.

Byte-Clk: A byte clock for a speed of 155.52 MHz with a speed of 19.44 MHz.

TCell-Req: Signal that notifies the sending side (AAL layer) whether the receiving side (ATM layer) receives

TCell-Sync: Signal to start transmission cell

TCell-Frm: Signal indicating valid section for transmission of transmitting cell

TCell-Clk: Combination of Byte-Clk and TCell-Frm, and signal that provides driving clock only in TCell-Frm section in synchronization with TCell-Sync.

TCell-Dat: 8-bit data signal transmitted in synchronization with Tcell-Sync, TCell-Frm, and TCell-Clk

RCell-Req: Signal that notifies the sending side (ATM layer) of the receiving side (AAL layer).

RCell-Frm: Signal indicating valid section for transmission of receiving cell

RCell-Clk: Signal that provides driving clock only in RCell-Frm section in synchronization with Byte-Clk, RCell-Frm and RCell-Sync.

RCell-Dat: 8-bit data signal transmitted in synchronization with RCell-Sync, RCell-Frm, and RCell-Clk

Therefore, as described above, the present invention, unlike the method of interfacing by the conventional synchronous method by the generation of asynchronous service data, transmits a service cell that occurs variably to the ATM layer and determines whether reception is performed at the other layer. It receives and transmits and prevents cell loss due to overflow of the buffer.T / RCell-Frm, which informs only the effective period of the cell, and T / RCell-Clk signal, which provides a clock only during the frame period, is applied to the clock and input enable signals. There is an advantage that can be used to connect ATM cells that are used asynchronously to the buffer driven by the clock and the buffer driven only by the clock at the AAL layer and the ATM layer.

Claims (1)

An ALL-side transmit buffer 12 for storing ATM cells from the ATM cell generating means 11 according to the cell clock, and a cell clock and a frame signal outputted from the ATM cell generating means 11 are received from the ATM layer. An ALL side transmission control means 13 which transmits a transmission clock to the ALL side transmission buffer 12 to transmit an ATM cell when the transmission request signal is received, and outputs a frame signal, a clock, and a synchronization signal to the ATM side; ATM layer side receiving buffer 14 receiving ATM cell from ALL side transmitting buffer 12 and receiving frame signal and clock from ALL side transmitting control block, and storage status signal from ATM layer side receiving buffer 14 And an ALL side reception control means 15 receiving a frame signal and a transmission clock from the ALL side transmission control means 13 and receiving a transmission request signal to the ALL side transmission control means 13, and ALL. By side When the transmission request signal is received from the ALL transmission buffer 19 and the ALL transmission buffer 19 storing the transmitted ATM cell, the transmission clock is transmitted to the transmission transmission buffer 19 at the ALL side to transmit the ATM cell and at the same time the frame signal and the clock. Inputs a frame signal, a clock, and a synchronization signal for providing an ATM side transmission control means 18 for transmitting a synchronization signal to the ALL side and a transmission request signal indicating whether or not reception is possible to the signal; ALL-side reception control means 17 for outputting a control signal instructing to output the received and received ATM cell, and output control from the ALL-side reception control means 17 when receiving an ATM cell from the ATM layer side. Asynchronous transmission mode (ATM) adaptation layer and asynchronous transmission, characterized in that it comprises an ALL-side receiving buffer 16 for outputting the stored ATM cell to the ATM cell processing means 20 when receiving a signal. De (ATM) matching control apparatus between layers.