KR960004327B1 - Tv frame format converting apparatus - Google Patents

Abstract

The apparatus has a circuit for converting a scanning format of an input video signal into a progressive scanning type if it is of an interlaced scanning type. A circuit converts the number of vertical scanning lines of an output video signal from this circuit into that of a display format. A circuit converts the number of horizontal pixels of an output video signal from the scanning line conversion circuit into that of the display format. A circuit controls the scanning format conversion circuit, the scanning line conversion circuit and the horizontal pixel conversions circuit to convert a frame format of the input video signal into the display format. The apparatus produces display format of monitor with no degradation of resolution.

Description

TV's Frame Format Converter

1 is a block diagram of a frame format conversion apparatus according to the present invention.

2 is an exemplary diagram of a frame conversion region.

3 is a timing diagram according to frame conversion.

4 is a detailed block diagram of a 3: 4 line conversion unit according to the present invention.

FIG. 5 is a detailed circuit diagram of the signal output control unit in FIG.

6 is a waveform diagram of each part in FIG. 5;

7 is a detailed block diagram of a 3: 4 pixel conversion unit according to the present invention.

8 is a waveform diagram of each part in FIG.

FIG. 9 is a detailed block diagram of another embodiment of the filter unit and the coefficient generator in FIG. 4; FIG. 10 is a waveform diagram of each unit in FIG.

11 is a detailed block diagram of a 4: 3 line conversion unit according to the present invention.

12 is a detailed circuit diagram of a first-in first-out control unit in FIG.

FIG. 13 is a waveform diagram of each part in FIG.

14 is a detailed block diagram of a 4: 3 pixel conversion unit according to the present invention.

FIG. 15 is a detailed circuit diagram of the signal selection control unit in FIG.

FIG. 16 is a waveform diagram of each part in FIG.

FIG. 17 is a detailed block diagram showing another embodiment of the filter unit and the coefficient generator in FIG.

FIG. 18 is a waveform diagram of each part in FIG. 17. FIG.

* Explanation of symbols for main parts of the drawings

1 line conversion unit 2 pixel conversion unit

3,21,53,69: filter part 4,40,54,86: line delay part

5,6,23,24,55,56,71,72: Multiplier

7,25,43,45,48,57,73,90,91,94,98,99: adder

8,26,58,74: signal output section 9,10,59: first-in, first-out memory

11,17,18,33,38,39,44,49,63,64,76,80,81,93,101: multiplexer

12: signal output control unit 13,34,61,78: coefficient generator

14,50,62,102: Line counter 15,36,52,66,67,84: Inverter

16,37,52,85: Andgate 19,35,65,79,82,83: 2-bit counter

20,68: Oagate 22, 27, 28, 30 to 32, 70: Latch

29,75: Demultiplexer 41,42,46,47,87 to 89,95 to 97: Divider

60: first-in, first-out control unit 77: signal selection control unit

The present invention relates to video format conversion of a TV, and more particularly, to a frame format conversion apparatus for a TV that performs frame format conversion without degrading an image resolution in a high-definition television (HDTV).

Recently, the high-definition TV standard of the United States has become visible to some extent, it is clear that the format for the video format is not limited to one, but to give a variety of formats to accommodate multiple formats.

That is, the frame format was limited to 787.5 lines of progressive scan format, 1050 lines of progressive scan and interlaced format. The main display format of the monitor was 787.5 lines of progressive scan format, and 1050 lines of interlaced formats were used in small monitors. It is expected that.

However, the active area of the sequential scan format of 787.5 lines is 1280 × 720 and the active area of sequential scan format of 1050 lines is 1728 × 960. In particular, the conversion between various formats has become an important issue in high definition TV systems in the US. .

In other words, even if any of the various video formats are transmitted from the broadcasting station, the monitor format of the receiver is fixed to one, so the video format must be converted to the monitor standard.

The present invention has been made of a frame format conversion apparatus of a TV that maintains a high resolution while lowering the manufacturing cost by implementing simple hardware to enable the conversion between video formats, which will be described in detail with reference to the accompanying drawings. same.

1 is a block diagram of a frame format conversion apparatus according to the present invention, as shown therein, a line converter 1 for converting a scan line of an input signal Vi, and an output of the line converter 1 ( V ₁ ) is configured as a pixel converter 2 for converting the number of pixels per line.

First, when the format is converted to the 3: 4 ratio, the line converter 1 and the pixel converter 2 are configured as follows.

As shown in FIG. 4, the line converter 1 includes a line delay unit 4 for delaying an input signal Vi, and a multiplier 5 for multiplying the input signal Vi by a coefficient K ₂ . ), A multiplier 6 multiplying the output V ₄ of the line delay unit 4 by a coefficient K ₁ , and an output V ₅ (V ₆ ) of the multiplier 5, 6. A first filter unit 3 comprising an adder 7, a first-in first-out memory 9 for temporarily storing the output V ₄ of the line delay unit 4, and an output V of the adder 7. ₇ ) a first-in, first-out memory 10 for temporarily storing the data, a multiplexer 11 for selectively outputting the outputs V ₉ and V ₁₀ of the first-in-first-out memory 9 and 10, and an output line clock CKO _1. The signal output control unit 12 outputs a read signal RD ₉ (RD ₁₀ ) to the first-in, first-out memory 9, ₁₀ , and outputs a selection signal Cl ₁₂ to the multiplexer 11. The input signal CKI ₁ is formed by the first signal output unit 8 and the synchronization signal Syn ₁ . The line counter 14 to count, the inverter 15 for inverting the output S ₀ of the line counter 14, the output of the inverter 15 and the output S ₁ of the line counter 14. The AND gate 16 for outputting the reset signal Reset to the line counter 14 by logical multiplication with the input counter A according to the output S ₀ and S ₁ of the line counter 14. ₁ , B ₁ , C ₁ ) (D ₁ , E ₁ , F ₁ ) are sequentially selected to output coefficients K ₁ (K ₂ ) to multipliers 6, 5 of the filter unit 3. It consists of a first coefficient generator 13 composed of a multiplexer (17) (18).

As illustrated in FIG. 7, the pixel converter 2 includes a latch unit 22 for latching an output V ₁₁ = V ₁ of the first signal output unit 8 for a predetermined time, and the input signal ( A multiplier 23 for multiplying V ₁ ) and a coefficient K ₄ , a multiplier 24 for multiplying the output V ₂₂ of the latch unit ₂₂ and a coefficient K ₃ , and the multiplier 23, 24. A second filter portion 21 comprising an adder 25 for summing the outputs of the < RTI ID = 0.0 >),< / RTI > latch portions 27 and 28 for sequentially latching the output V ₂₂ of the latch portion 22 for a predetermined time; 1 × 3 demultiplexer 29 for selecting three outputs V ₂₅ of the adder 25 and latch portions 30 and 31 for latching the outputs V ₂₉₁ and V ₂₉₂ of the demultiplexer 29 for a predetermined time. ), And 4 × 1 for combining and outputting the outputs V ₂₈ (V ₃₁ ) (V ₃₂ ) of the latch units 28, 31, and ₃₂ and the output V ₂₉₃ of the demultiplexer 29. and a second signal output section 26 is composed of a multiplexer (33), for counting the input sample clock (CKS) by a synchronization signal (Syn ₁₎ 2 ratio Counter 35 and the output of the output and the counter 35 of the counter 35, the output inverter 36, the inverter 36 for inverting the (S ₀₎ for (s _1), the logic multiplying the counter An AND gate 37 for outputting a reset signal Reset to 35 and an input coefficient A ₂ , B ₂ , C ₂ depending on the outputs S ₀ , S ₁ of the counter 35. Multiplexer 38 for sequentially selecting (D ₂ , E ₂ , F ₂ ) and outputting each coefficient K ₃ (K ₄ ) to multipliers 24 and 23 of the filter unit 2l ( And a second coefficient generator 34 composed of 39).

As another embodiment of the line converter 1, the first filter unit 3 and the first coefficient generator 13, as shown in FIG. 9, delay the line of the input signal Vi to delay the first signal. Each of the line delay unit 40 and the input signal Vi which are output to the first-in first-out memory 9 of the output unit 8 and the input signal Vi are respectively 1/4. The divider 46, 47 which averages 1/2, the adder 48 which sums the outputs of the divider 46, 47, and the output of the line delay unit 40 (V ₄₀ ) Dividers 41 and 42 for averaging 1/4 and 1/2, adders 43 for summing outputs of the dividers 41 and 42, and the dividers 41 and 42 and adders. A multiplexer 44 for selectively outputting the output of the 43 according to the control signals S ₀ and S ₁ , and the outputs of the adders 48 and the dividers 47 and 46 are controlled by the control signals S ₀ and S 1. ₁ ) replaces the multiplexer 49 for selective output with the adder 45 for summing the outputs of the multiplexers 44 and 49 and outputting them to the first-in-first-out memory 10 of the first signal output unit 8. To configure.

In the case of converting the format to 4: 3 ratio, the line converter 1 includes a multiplier 55 for multiplying the coefficient K _{6 by the} input signal Vi, as shown in FIG. A line delay unit 54 for line delaying the input signal Vi, a multiplier 56 for multiplying the output of the line delay unit 54 and the coefficient K ₅ , and the multipliers 55 and 56 A third filter unit 53 comprising an adder 57 for summing outputs, a first-in first-out memory 59 for temporarily storing the output V ₅₇ of the third filter unit 53, and a line clock CKI ₂ A third signal output unit 58 comprising a first-in first-out control unit 60 for outputting the write clock WR ₃₄ to the first-in first-out memory 59 and an input clock CKI ₂ by a synchronization signal Syn. ), And the input counters A ₃ , B ₃ , C ₃ , D ₃ (E ₃ , F) according to the line counter 62 for counting) and the outputs S ₀ , S ₁ of the line counter 62. _3, G _3, H ₃₎ the product of the sequentially selected by repeating the filter unit 53 Constitute a group 56, 55, the coefficient (K _5), a third coefficient consisting of a multiplexer 63, 64 for respectively outputting a (K ₆₎ generating unit 61 to the.

As illustrated in FIG. 14, the pixel converter 2 includes a multiplier 71 for multiplying the output V ₅₉ of the third signal output unit 58 by a coefficient K ₈ , and the input signal ( A latch unit 70 for latching V ₅₉ ) for a predetermined time, a multiplier 72 multiplying the output of the latch unit 70 by a coefficient K ₇ , and an output of the multipliers 71 and 72. Fourth filter section 69 made up of adder 73, a 1x4 demultiplexer 75 for selecting four outputs V ₇₃ of the filter section 69, and three of the outputs of the demultiplexer 75. Signals for controlling the 1 * 4 demultiplexer 75 and the 4 * 1 multiplexer 76 according to the 4 * 1 multiplexer 76 outputting only the dogs, the input sample clock CSI ₁ and the output sample clock CSO ₁ . A fourth signal output section 74 composed of the selection control section 77, a 2-bit counter 79 for counting the input sample clock CSI ₁ by the synchronization signal Syn ₂ , and an output of the counter 79 According to (S ₀ , S ₁ ), each input coefficient (A ₄ , B ₄ , C ₄ , D ₄ ) (E ₄ , F ₄ , G ₄ , H ₄ ) are repeatedly selected in order to multiply coefficients K ₇ and K ₈ in multipliers 72 and 71 of the filter section 69. The fourth coefficient generation unit 78 is composed of a multiplexer (80, 81) for outputting.

As another embodiment of the line converter 1, the third filter unit 53 and the third coefficient generator 61 output the input signals Vi as shown in FIG. 17, respectively. Dividers 95 and 96 and 97 for averaging / 4 and 1/2, adders 98 for summing outputs of the dividers 96 and 97, and the dividers 95 and 96 An adder 99 for summing the outputs of the output, the subtractor 95, a subtractor 100 for calculating the output difference of the adder 98, and the outputs S ₀ and S ₁ of the line counter 102. A multiplexer 101 for combining the ground GND, the output of the adder 99, the output of the subtractor 100, and the voltage Vcc, and a line delay unit for delaying the input signal Vi. 86, dividers 87, 88 and 89 that average the outputs of the line delay unit 86 by 1/16, 1/4 and 1/2, respectively, and the dividers 88 and 89, respectively. The difference between the output of the adder 90 and the divider 87 and the adder 90, which adds the outputs of the adder 90 and the outputs of the dividers 87 and 88. The ground GND, the output of the adder 91, the output of the subtractor 92, and the voltage Vcc according to the adder 92 to be calculated and the outputs S ₀ and S ₁ of the line counter 102. The combined multiplexer 93 and the outputs of the multiplexers 93 and 101 are added and replaced by an adder 94 that outputs to the first-in, first-out part 59 of the third signal output unit 58.

If described in detail with reference to the accompanying drawings the operation and effect of the present invention configured as follows.

As shown in FIG. 2, in the case of conversion between frame formats of an image, as shown in FIG. 1, an input signal Vi is input to the line converting section 1 to convert the number of scanning lines, and the number of scanning lines is converted. The converted signal V ₁ is converted into a frame format as the pixel per line is sampled through the pixel converter 2.

First, in the case of 3: 4 ratio conversion for converting a format having an active area of 1280 × 720 to a format having 1728 × 960, the circuits of FIGS. 4 and 7 are applied to the line converter 1 and the pixel converter 2. As the phases of the clocks are compared, the positions of the input lines and the relative output lines are compared to apply a weighted averaging method of the surrounding input lines. Referring to FIG. Because of the overlap, the first input line is output as is and the second output line spans the first and second input lines but is located close to the second line, giving weight to the second line.

That is, the second output line Y (2) = 0.25X (1) + 0.75X (2) can be calculated, and the third and fourth output lines are similarly calculated. After the fourth line, the above operation is performed from the fifth line. The general interpolation is as follows and for the 3: 4 transformation K ₁ is repeatedly described as 1, 0.75, 0.5, 0.25.

Y (n) = K ₁ X (n) + K ₂ X (n + 1)

K ₁ + K ₂ = 1

In this case, in the line converter 1 receiving the format signal Vi of 720 lines, the first coefficient generator 13 inputs the input clock CKI ₁ and the synchronization signal Syn ₁ to the line counter 14. ) Outputs control signals S ₀ and S ₁ by counting the input clock CKI ₁ , and each of the multiplexers 17 and 18, which receives the control signals S ₀ and S ₁ , respectively. The input coefficients A ₁ , B ₁ , C ₁ (D ₁ , E ₁ , F ₁ ) are repeatedly selected in order to multiply the coefficients K ₁ (K ₂ ) by the multiplier 6 of the first filter part 3. Each of them will be output to (5).

Here, the first output (K ₁₎ (K ₂₎ is a period of 3 lines K ₁ is 0.25, 0.5, 0.75 the value is sequentially repeated K ₂ is 0.75, 0.5, 0.25 of the coefficient generator 13 The values are repeated sequentially, inserting the first input line every three lines for a 3: 4 ratio conversion.

Then, as the line counter 14 counts the input clock CKI ₁ , the control signal S ₀ is inverted in the inverter 15, and the inversion signal is logically multiplied with the control signal S1 in the AND gate 16. The input signal is input to the line counter 14 as a reset signal. When the input of every three lines is completed, the multiplexers 17 and 18 clear the line counter 14 before the fourth line is input. Each input coefficient (A ₁ , B ₁ , C ₁ ) (D ₁ , E ₁ , F ₁ ) is sequentially selected for every three lines.

Accordingly, the signal Vi input to the line converter 1 is input to the first filter unit 3, multiplied by the coefficient K ₂ in the multiplier 5, and simultaneously delayed by the line delay unit 4. After that, it is stored in the first-in first-out memory 9 of the first signal output unit 8 and multiplied by the coefficient K ₁ in the multiplier 6, and the outputs of the multipliers 5 and 6 are summed in the adder 7. And then stored in the first-in, first-out memory 10 of the first signal output unit 8.

In this case, the first-in, first-out memory 9 and 10 output the output V ₄ and V ₇ of the first filter unit 3 to the output RD ₉ of the signal output control unit 11 according to the output line clock CKO ₁ . After storing according to RD ₁₀ , the multiplexer 11 controlled by the output C1 ₁₂ of the signal output controller 11 selectively outputs the outputs of the first-in, first-out memory 9, 10. .

That is, the signal output control unit 12 outputs the read signal RD ₉ (RD ₁₀ ) as shown in FIG. 6 (b) (c) to the first-in, first-out memory 9, 10, and at the same time, As shown in FIG. 5, as shown in FIG. 5, an output clock CKO ₁ such as FIG. 6 (a) is counted in the 2-bit counter 19 so that the output is logically summed in the oragate 20. The selection signal C1 ₁₂ as shown in FIG. 6 (d) is output to the multiplexer 11.

Here, the first-in-first-out memory 9 stores only the first line and outputs it according to the speed, and the first-in, first-out memory 10 stores the weighted averaged signal and outputs it according to the speed. To prevent the underflow of the memory, one memory stops the storage operation when one memory is stored.

Accordingly, when the output (V ₁ = V ₁₁ ) of the line converter ₁ is input to the pixel converter 2, the second coefficient generator 34 performs an input sample clock (CKS) as shown in FIG. 8A. ) And the synchronization signal (Syn ₁ ) are received and the control signal (S ₀ , S ₁ ) is output by counting the input sample clock (CKS) in the 2-bit counter 35 and this control signal (S ₀ , S ₁ ) Each multiplexer (38) (39) receives the input coefficients (A ₂ , B ₂ , C ₂ ) (D ₂ , E ₂ , F ₂ ) to sequentially select the coefficient (K ₃ ) (K ₄ ) are respectively output to the multipliers 24 and 23 of the second filter unit 21.

Here, as the 2-bit counter 35 counts the input sample clock CKS, the output S ₀ is inverted at the inverter 36 and logically multiplied at the output S ₁ and the question 37 to form the line. A reset signal Reset is output to the counter 35. When the input of every three pixels is completed, the coefficient selection operation of the multiplexers 38 and 39 is controlled by clearing the counter 35 before the fourth pixel is input. Done.

In this case, the second filter unit 21 receives the output V ₁₁ of the first signal output unit 8 and multiplies the coefficient K ₄ by the multiplier 23, and the input signal V ₁₁ is a latch unit ( 22 is latched for a predetermined time and input to the second signal output unit 26, and the coefficient K ₃ is multiplied by the multiplier 24, and the output of the multiplier 24 is added through the adder 25. It is summed with the output of (23) and then input to the second signal output section (26).

Accordingly, the second signal output section 26 transfers the latch section 22 output V ₂₂ of the second filter section 21 from the latch section 27 to the clock CK _{27 as} shown in FIG. an output (V ₂₅₎ of a predetermined time the output (V ₂₈₎ of retaining and then through the latch portion 28 and the eighth degree (c) and input to the 4 × 1 multiplexer 33, the adder 25 in accordance with 1 × After selecting three by three through the demultiplexer 29, the first output V ₂₉₁ sequentially inputs the latch units 30 and 31 to the 4x1 multiplexer 33 as shown in FIG. The second output V ₂₉₂ is input to the 4x1 multiplexer 33 as shown in FIG. 8 (e) through the latch portion 32, and the third output V ₂₉₃ as shown in FIG. By inputting to the 4x1 multiplexer 33, the multiplexer 33 controlled to an output clock CKO _{2 as} shown in FIG. 8h is pixel-converted at a 3: 4 ratio as shown in FIG. 8g. The signal V ₃₃ is output.

Also, as another embodiment of the 3: 4 ratio conversion of the present invention, as in the circuit of FIG. 9, the first filter unit 3 and the first coefficient generator 13 of FIG. 4 are replaced with the line converter 1 The signal Vi of 720 lines is inputted to the signal, and averaged 1/4 and 1/2 through the dividers 46 and 47, and are summed through the adder 48, and the output and divider of the adder 48 ( The outputs of 47 and 46 are input to the multiplexer 49 and the input signal Vi is line delayed through the line delay unit 40 and then stored in the first-in first-out memory 9 of the first signal output unit 8. In addition, the average of 1/4 and 1/2 through the dividers 41 and 42 are summed in the adder 43, and the outputs of the dividers 41 and 42 and the output of the adder 43 are multiplexer 44. Is entered.

At this time, the line counter 50 counts the line clock as shown in FIG. 10 (a), and gives the multiplexer 44 and 49 a control signal S ₀ (S ₁ ) as shown in FIG. 10 (c) (d). The first-in first-out memory 10 of the first signal output unit 8 after the multiplexers 44 and 49 are summed by the adder 45, as shown in FIG. )

Here, as the line counter 50 counts the input clock as shown in FIG. 10 (a), the output S ₀ is inverted in the inverter 51 and logically multiplied in the output S ₁ and the question 16. By outputting a reset signal (Reset) to the line counter 50, the multiplexer 44 (49) by clearing the count value of the line counter 50 before the fourth line is input when every three line input is completed. ) To control the operation.

Therefore, the multiplexer 11 selects and outputs the outputs of the first-in, first-out memory 9 and 10 according to the output C1 ₁₂ of the signal output control unit 12 and the line-converted signal of the first signal output unit 8. (V ₁₁₎ is the pixel-per-line via the pixel converting unit (2) 3: is the format converted into a signal having an active region of 1728 × 960 and then finally converted to 4 ratio.

On the other hand, in the case of 4: 3 ratio conversion in which a format having an active region of 1728 × 960 is converted to a format of 1280 × 720, the circuits of FIGS. 11 and 14 are applied to the line converter 1 and the pixel converter 2. When the format signal Vi of 960 lines is input to the third filter unit 53, the third coefficient generator 61 receives an input clock CKI ₂ and a synchronization signal Syn ₂ , and receives a line counter 62. In order to output the control signals S ₀ and S ₁ by counting the input clock CKI ₂ , the multiplexers 63 and 64 receiving the control signals S ₀ and S ₁ are each input coefficient A. ₃ , B ₃ , C ₃ , D ₃ ) (E ₃ , F ₃ , G ₃ , H ₃ ) are repeatedly selected in order to multiply the coefficients K ₅ (K ₆ ) by the multiplier of the third filter unit 53. (56) and (55).

At this time, the output K ₅ (K ₆ ) of the third coefficient generator 61 has a value of 1, 0.67, 0.33, 0 for K ₅ , and K ₆ for ø, 0.33, 0.67, 1 for 4 line cycles. Repeatedly set sequentially, if the value is '' 0 '' in the fourth line as the unnecessary line is removed.

Accordingly, the signal Vi input to the line converting unit 1 is input to the third filter unit 53 and multiplied by the coefficient K ₆ in the multiplier 55, and at the same time the line via the line delay unit 54. After being delayed, the multiplier 56 multiplies the coefficient K ₅ and the outputs of the multipliers 55 and 56 are summed in the adder 57 and then the first-in, first-out memory 59 of the third signal output unit 58. Are stored in.

In this case, the first-in first-out memory 59 stores and outputs the output V ₅₇ of the third filter unit 53 according to the output of the first-in first-out control unit 60. As the input line clock CKI ₂ as shown in FIG. 13 (a) is counted by the 2-bit counter 65, the outputs are inverted in the inverters 66 and 67, respectively, and logically summed in the oragate 68. The write clock WR ₃₄ as shown in FIG. 13B outputs to the first-in, first-out memory 59.

That is, according to the output of the first-in first-out control unit 60, the first-in first-out memory 59 does not store one line every four lines of the output of the third filter unit 53 to perform 4: 3 ratio line conversion. do.

When the output (V ₁ = V ₅₉ ) of the line converter ₁ is input to the pixel converter 2, the fourth coefficient generator 78 may generate an input sample clock (CSI ₁ ) as shown in FIG. ) And the synchronization signal (Syn ₂ ) are received and the control signal (S ₀ ), (S ₁ ) is output as the input sample clock (CSI ₁ ) is counted in the 2-bit counter 79 and this control signal (S ₀₎ The multiplexers 80 and 81 that receive the inputs S ₁ and S are repeatedly selected sequentially from the input coefficients A ₄ , B ₄ , C ₄ , D ₄ (E ₄ , F ₄ , G ₄ , H ₄ ). The coefficients K ₇ and K ₈ are output to the multipliers 72 and 71 of the third filter unit 69.

Accordingly, the fourth filter unit 69 receives the output V ₅₉ of the third signal output unit 58 and multiplies the coefficient K ₈ by the multiplier 71, and the input signal V ₅₉ is a latch unit. After a predetermined time latching through 70, the multiplier 72 multiplies the coefficient K ₇ and the outputs of the multipliers 71 and 72 are summed in the adder 73, and then the fourth signal output unit 74 Is entered.

At this time, the fourth signal output unit 74 receives the output (V ₇₃ ) of the fourth filter unit 69, selects four from the 1x4 demultiplexer 75, and combines them through the 4x1 multiplexer 76. Outputs a pixel-converted signal at a 4: 3 ratio, and the 1 × 4 demultiplexer 75 and the 4 × 1 multiplexer 76 are controlled by the control outputs S ₇₅ and S ₇₆ of the signal selection controller 77. Controlled.

That is, the signal selection controller 77 configured as shown in FIG. 15 calculates the input signal clock CSI ₁ as shown in FIG. 16 (a) by the 2-bit counter 82 and counts the control signal S _{75 as a} 1x4 multiplexer. As shown in (75), four outputs V ₇₃ of the fourth filter unit 69 are selected four by the timing shown in FIGS. 16 (b) to (e) and shown in FIG. 16 (h). As the 2-bit counter 83 counts the output sample clock CSO ₁ as one and outputs the control output S76 as shown in FIG. 16 (f), the 4x1 multiplexer 76 is set to 1 as described above. Only three of the outputs V _751- V _{754 of the x4} multiplexer 75 are sequentially selected and output as shown in Fig. _16G .

Here, the signal selection control unit 77 outputs the control signal S ₇₆ by counting the output sample clock CSO ₁ by the 2-bit counter 83 and output S ₀ is inverted by the inverter 84. The gate 85 outputs a reset signal Reset to the 2-bit counter 83 by being multiplied by the output S _{1. The} 3-bit counter 83 is cleared after a three-pixel count so that the 4 × 1 multiplexer is cleared. Reference numeral 76 outputs the 4: 3 pixel converted signal V ₇₆ by removing the fourth output of the 1x4 demultiplexer 75, that is, removing the fourth pixel every four pixels.

In addition, when the fourth filter unit 53 and the fourth coefficient generator 61 of FIG. 11 are replaced by the circuit of FIG. 17 of the 4: 3 ratio conversion of the present invention, 960 lines of signals (V) are applied to the line converter 1. _i ) is inputted and averaged 1/16, 1/4, 1/2 through the dividers 95, 96 and 97, and then the outputs of the dividers 96 and 97 are summed in the adder 98. The outputs of the dividers 95 and 96 are summed in the adder 99, the output of the divider 95 and the output of the adder 98 are input to the subtractor 100, and the difference is calculated. The outputs of the subtractor 100 and the adder 99 are respectively input to the second and third inputs of the multiplexer 101 whose fourth input is connected to ground GND and the voltage Vcc.

Then, the input signal Vi is output as shown in FIG. 18B through the line delay unit 86 so that the averages of 1/16, 1/4, and 1/2 in the dividers 87, 88, and 89 are obtained. And then the outputs of the dividers 88 and 89 are added in the adder 90 and the outputs of the dividers 87 and 88 are added in the adder 91 and the dividers 88 in the subtractor 92. Output difference between the output of the adder 90 and the adder 90 and the first and fourth inputs of the adder 91 to the second and third inputs of the multiplexer 93 connected to the voltage Vcc and the ground GND. The output of the subtractor 92 is input.

At this time, in the line counter 102 that counts the line clock as shown in FIG. 18 (a), the control output S ₀ (S ₁ ) as shown in FIG. 18 (c) (d) is multiplexer 93 (101). As shown in FIG. 18 (e) (f), the output V ₉₃ and V ₁₀₁ are summed in the adder 94 and then stored in the first-in first-out memory 59 of the third signal output unit 58. Lose.

Accordingly, the first-in first-out control unit 60 controls the first-in first-out memory 59 to output the signal V ₅₉ removed by one line, and the line-converted signal V ₅₉ is lined through the pixel converter 2. The pixels are converted into a 4: 3 ratio and then finally converted into a signal having an active area of 1280x720.

As described in detail above, the frame format converting apparatus of the present invention can be easily applied to a high definition TV (HDTV) in the future by lowering the manufacturing cost by implementing a simple hardware without degrading the resolution.

Claims (18)

In a TV that converts a 787.5-line scan format into a 100-line scan format, the input clock CKI ₁ is counted according to the synchronization signal Syn ₁ , and the input coefficients A ₁ , B ₁ , and C ₁ are repeated _every three lines. The first coefficient generator 13 repeatedly outputting (D ₁ , E ₁ , F ₁ ) sequentially and outputting the adaptive coefficient K _l (K ₂ ), and delaying the input signal Vi signal (V ₄₎ is multiplied by a coefficient (K ₁₎ in multiplied by a coefficient (K ₂₎ to the input signal (Vi) and the operation signal (K ₁ V ₄₎ calculating a weighted average by summing the (K ₂ V _i) The first filter unit 3 for line interpolation and the cnf force V ₄ (V ₇ ) of the first filter unit 3 is temporarily stored and output according to the output line clock CKO ₁ . A line converter 1 having one signal output unit 8 for outputting four interpolated lines every three lines, and counting the input sample clocks CKS according to the synchronization signal Syn ₁ to cycle the three pixels. input coefficients _{(a 2, B 2, C} 2) (D 2, E 2, F 2) the Derivative by repeating selected adaptive coefficient (K ₃₎ (K ₄₎ for the output a second coefficient generator (34) for, the output signal (V ₁₁₎ of the first signal output portion 8, a certain amount of time latched signal (V ₂₂₎ is multiplied by a coefficient (K ₂₎ for multiplying the coefficients (K ₄₎ to the output signal (V ₁₁₎ and the operation signal _{(K 3 V 22) (K} 4 V 11) two pixels adjacent by summing the The second filter unit 21 which calculates an adaptive weighted average between the pixels and performs interpolation filtering, latches the output V ₂₂ of the second filter unit 21, and separates the output V ₂₅ to produce a combined output. And a pixel converter (2) for interpolating four pixels every three pixels, with a second signal output section (26). The first coefficient generator 13 includes a line counter 14 that counts the input clock CKI ₁ according to the synchronization signal Syn ₁ and outputs control signals S ₀ and S ₁ . According to the output (S ₀ ) (S ₁ ) dp of the line counter 14, each input coefficient (A ₁ , B ₁ , C ₁ ) (D ₁ , E ₁ , F ₁ ) is sequentially selected and Multiplexers 17 and 18 respectively outputting to one filter section 3 with adaptive coefficients K ₁ and K ₂ , and inverter 15 for inverting the output S ₀ of the line counter 14. And an AND gate 16 which outputs a reset signal Reset to the line counter 14 by ANDing the output signal of the inverter 15 and the output signal S _{1 of} the line counter 14. TV frame format converter characterized in that. 2. The filter of claim 1, wherein the first filter unit 3 multiplies the multiplier 5 by multiplying the input signal Vi by the output K ₂ of the first coefficient generator 13 and the input signal V ₁ . A line delay unit 4 for outputting the delay signal V ₄ to the first signal output unit 8 by delaying the line, and the first coefficient generating unit at an output V ₄ of the line delay unit 4. A multiplier (6) multiplying the output (K ₁ ) of (13) and the outputs of the multipliers (5) and (6) are added to output the sum signal (V ₇ ) to the first signal output unit (8). Adder (TV frame format converter, characterized in that consisting of a group. The signal output controller of claim 1, wherein the first signal output unit 8 outputs a read signal RD ₉ (RD ₁₀ ) and a select signal Cl ₁₂ as the output line clock CKO ₁ is counted. 12 and a first-in first-out memory 9 for temporarily storing the output V ₄ and V ₇ of the first filter unit 3 in accordance with the outputs RD ₉ and RD ₁₀ of the signal output control unit 12. And a multiplexer 11 that selects an output of the first-in first-out memory 9 and 10 according to the output Cl ₁₂ of the signal output control unit 12 and outputs the output to the second filter unit 21. TV frame format converter characterized in that the configuration. The 2-bit counter 35 according to claim 1, wherein the second coefficient qkf generator 34 counts the input sample clock CKS according to the synchronization signal Syn ₁ and outputs a control signal S ₀ (S ₁ ). ) And the respective input coefficients A ₂ , B ₂ , C ₂ (D ₂ , E ₂ , F ₂ ) are sequentially repeated according to the output S ₀ (S ₁ ) of the 2-bit counter 35. Inverters for selecting and inverting the output S ₀ of the line counter 35 and the multiplexers 38 and 39 for selecting and respectively outputting adaptive coefficients K ₃ and K ₄ to the second filter unit 21. And an AND gate 37 which multiplies the output of the inverter 36 and the output S _{1 of} the line counter 35 to output a reset signal Reset to the line counter 35. TV frame format converter characterized in that the configuration. The multiplier (23) according to claim 1, wherein the second filter part (21) is multiplied by the multiplier (23) multiplying the output (V ₁₁ ) of the first signal output part (8) by the output (K ₄ ) of the second coefficient generator (34). And a latch unit 22 for latching the input signal V ₁₁ for a predetermined time and outputting the second signal output unit 26 to the second signal output unit 26, and the second coefficient generating unit at the output V ₂₂ of the latch unit 22. A multiplier 24 for multiplying the output K ₁ of (34) and an adder 25 for summing the outputs of the multipliers 23 and 24 and outputting them to the second signal output unit 26. TV Frame Format Inverter. The second signal output unit 26 includes a latch unit 27 and 28 for sequentially latching the output V _{22 of} the second filter unit 21, and the second filter unit 21. of the output (V _25), the third by one select signal (V ~V _{291 293)} and 1 × 3 demultiplexer 29 to output to, the 1 × 3 to sequentially latch the first output ₍₂₉₁ V) of the demultiplexer 29 the output of the latch section 30, 31 and the latch portion 32 and the latch portion 28 (31, 32) for latching the second output (V ₂₉₂₎ of the multiplexer (29) (V ₂₈₎ (V ₃₁₎ (V ₃₂₎ and the frame format conversion apparatus of the television to the third output ₍₂₉₃ V) of the demultiplexer 29, characterized in that it consists of a 4 × 1 multiplexers 33 for combining the output. The first filter unit 3 and the first coefficient generator 13 include dividers 46 and 47 for averaging the input signals Vi by 1/4 and 1/2. An adder 48 that sums the outputs of the adders 46 and 47, and the output of the adder 48 and the output of the dividers 47 and 46 in sequence according to the control signals S ₀ and S ₁ . A line delay unit 40 for selecting and outputting a multiplexer 49, a line delay of the input signal Vi, and outputting the first signal output unit 8 to the first-in first-out memory 9; A divider (41) (42) for averaging the output (V ₄₀ ) of ( ₄₀ ) 1/4, 1/2, an adder (43) for summing the outputs of the dividers (41) (42), and A multiplexer 44 for sequentially selecting and outputting the outputs of the dividers 41 and 42 and the adder 43 according to the control signals S ₀ and S ₁ , and the outputs of the multiplexers 44 and 49 are added up. The adder 45 outputting to the first-in first-out memory 10 of the first signal output unit 8, the line clock, and the control signal S ₀ , The line counter 50 for outputting (S ₁ ), the inverter 51 for inverting the output S ₀ of the line counter 50, the output of the inverter 51 and the line counter 50 And an AND gate (52) for outputting a reset signal (Reset) to the line counter (50) by performing an AND operation on the output (S1). In a TV that converts a scanning format of 1050 lines into a scanning format of 787.5 lines, the input clock CKI ₂ is counted according to the synchronization signal Syn ₂ , and the respective input coefficients A ₃ , B ₃ , and C are cycled. ₃ , D ₃ ) (E ₃ , F ₃ , G ₃ , H ₃ ) to sequentially select the third coefficient generator 61 for outputting the adaptive coefficient (K ₅ ) (K ₆ ) and the input signal the (V _i) to the line delayed signal multiplied by the coefficient (K ₅₎ as multiplied by the coefficient (K ₆₎ to the input signal (V _i) summing the operation signal _{(K 5 Vi) (K 6} Vi) A third filter unit 53 that obtains a weighted average by using the third filter unit 53 and a third V4 temporarily storing and outputting three of the outputs V ₅₇ of the third filter unit 53 according to the input line clock CKI ₂ . A line converter 1 having a signal output unit 58 for outputting three lines every four lines, and counting the input sample clock CSI ₁ in accordance with the synchronization signal Syn ₂ to cycle each of the four pixels. Input coefficients (A ₄ , B ₄ , C ₄ , D ₄ A fourth coefficient generator 78 which sequentially selects (E ₄ , F ₄ , G ₄ , H ₄ ) and outputs it as adaptive coefficients K ₇ (K ₈ ), and the second signal output unit the output (V ₅₉₎ of 58 is multiplied by the coefficient (K ₈₎ adjacent by multiplying the coefficient (K ₇₎ to the output (V ₅₉₎ of the second signal output portion (58) summing the calculated signal The fourth filter unit 69 calculates a weighted average between two pixels, and selects four outputs V ₇₃ of the fourth filter unit 69 according to the input sample clock CSI ₁ to output only three. And a pixel converter (2) having a fourth signal output unit (74) for filtering every three pixels into three pixels. The third coefficient generator 61 includes a line counter 62 that counts the input clock CKI ₂ according to the synchronization signal Syn ₂ , and an output S ₀ of the line counter 62. The third filter unit 53 by sequentially selecting each of the input coefficients A ₃ , B ₃ , C ₃ , D ₃ according to (S ₁ ), sequentially and repeatedly selecting (E ₃ , F ₃ , G ₃ , H ₃ ). And a multiplexer (63) (64) respectively outputting adaptive coefficients (K ₅ ) and (K ₆ ) to the TV frame format converter. The method of claim 9, wherein the third filter portion 53 is the input signal and the output (K _6), a multiplier 55 for multiplying a third coefficient generator 61 to the (V _i), the input signal (V _i) A line delay unit 54 for delaying a line, a multiplier 56 for multiplying the output of the line delay unit 54 by the output K ₅ of the third coefficient generator 61, and the multiplier 55. And an adder (57) for summing the outputs of the (56) to the third signal output unit (58). 10. The first-in first-out control unit 60 according to claim 9, wherein the third signal output unit 58 counts the line output CKI _{2 and} outputs the light clock WR ₂₄ . According to the output WR ₃₄ , the frame format of the TV comprising a first-in first-out memory 59 that temporarily stores the output V ₅₇ of the third filter unit 53 and outputs only three of four lines. Inverter. 13. The first-in first-out control unit 60 according to claim 12, wherein the first-in first-out control unit 60 includes a 2-bit counter 65 for counting the line clocks CKI ₂ and inverters 66 and 67 for inverting the output of the 2-bit counter 65, respectively. And an orifice (68) for outputting the write clock (WR ₃₄ ) to the first-in, first-out memory (59) by ORing the outputs of the inverters (66) and (67). The second coefficient generator 78 is a 2-bit counter 79 that counts the input sample clock CSI ₁ according to the synchronization signal Syn ₂ , and an output of the 2-bit counter 79. According to S ₀ ) (S ₁ ), each input coefficient (A ₄ , B ₄ , C ₄ , D ₄ ) (E ₄ , F ₄ , G ₄ , H ₄ ) is repeatedly selected in order to sequentially select the fourth filter unit ( And a multiplexer (80) (81) for outputting adaptive coefficients (K ₇ ) and (K ₈ ) respectively. The multiplier 71 according to claim 9, wherein the fourth filter unit 69 multiplies the output V ₅₉ of the third signal output unit 58 by the output K ₈ of the fourth coefficient generation unit 78. The multiplier 72 multiplies the latch unit 70 for latching the input signal V ₅₉ for a predetermined time and the output K ₇ of the fourth coefficient generation unit 78 to the output of the latch unit 70. And an adder (73) for summing the outputs of the multipliers (71) (72) and outputting them to the fourth signal output unit (74). The signal selection controller of claim 9, wherein the fourth signal output unit 74 counts the input sample clock CSI ₁ and the output sample clock CSO ₁ and outputs a control signal S ₇₅ (S ₇₆ ). 77, a 1x4 demultiplexer 75 which selects four outputs V ₇₃ of the fourth filter unit 69 according to the output S ₇₅ of the signal selection control unit 77, and the signal selection control unit. 77, the output (S _76), the frame format conversion apparatus of the television, characterized in that consists of a 4 × 1 multiplexers 76 that select the output only three of the output of the demultiplexer 75 sequentially according to the. The signal selection control unit 77 according to claim 16, wherein the signal selection control unit 77 outputs a control signal S ₇₅ to the 1 * 4 demultiplexer ₇₅ as the input sample clock CSI ₁ is counted, and an output. The 2-bit counter 83 outputs the control signal S ₇₆ to the 4 * 1 multiplexer ₇₆ as the sample clock CSO ₁ is counted, and the output S ₀ of the 2-bit counter 83 is inverted. And an AND gate for outputting a reset signal Reset to the 2-bit counter 83 by performing an AND operation on the inverter 84 and the output of the inverter 84 and the output S _{1 of} the 2-bit counter 83. TV frame format converter, characterized in that consisting of (85). The divider (95) (96) of claim 9, wherein the third filter unit (53) and the third coefficient generator (61) average the input signal (V _i ) by 1/16, 1/4, 1/2. ), An adder 98 for summing the outputs of the dividers 96 and 97, an adder 99 for summing the outputs of the dividers 95 and 96, and the divider ( 95 and a subtractor 100 for calculating an output difference between the adder 98, the ground GND, the output of the subtractor 100, and the adder 99 according to the control signal S ₀ (S ₁ ). and the output and voltage (Vcc), a multiplexer 101 that sequentially selected, and the line delay unit 86 to delay lines for the input signal (V _i), the output of the line delay unit 86 1/16 , Dividers 87, 88 and 89 for averaging 1/4 and 1/2, adders 90 for summing outputs of the dividers 88 and 89, and the dividers 87 ( An adder 91 for summing outputs of the 88, a subtractor 92 for calculating an output difference between the divider 87 and the adder 91, and a voltage according to the control signal S ₀ (S ₁ ). (Vc c), a multiplexer 93 for sequentially selecting an output of the adder 91, an output of the subtractor 92, and a ground GND, and an output of the multiplexers 94 and 101 to add up a third signal; The adder 94 for outputting to the output unit 74 and the line counter 102 for outputting a control signal S ₀ (S ₁ ) to the multiplexer 93 and 10 as the line clock is counted. TV frame format converter characterized in that the configuration.