KR960002030A - Multi Interrupt Communication Circuit - Google Patents

Multi Interrupt Communication Circuit Download PDF

Info

Publication number
KR960002030A
KR960002030A KR1019940015573A KR19940015573A KR960002030A KR 960002030 A KR960002030 A KR 960002030A KR 1019940015573 A KR1019940015573 A KR 1019940015573A KR 19940015573 A KR19940015573 A KR 19940015573A KR 960002030 A KR960002030 A KR 960002030A
Authority
KR
South Korea
Prior art keywords
interrupt
intelligent module
microcomputer
communication circuit
flop
Prior art date
Application number
KR1019940015573A
Other languages
Korean (ko)
Other versions
KR100244885B1 (en
Inventor
이정열
성석경
Original Assignee
경주현
삼성중공업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경주현, 삼성중공업 주식회사 filed Critical 경주현
Priority to KR1019940015573A priority Critical patent/KR100244885B1/en
Publication of KR960002030A publication Critical patent/KR960002030A/en
Application granted granted Critical
Publication of KR100244885B1 publication Critical patent/KR100244885B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
  • Computer And Data Communications (AREA)

Abstract

본 발명은 다중인터럽트통신회로에 관한 것이다. 본 발명의 다중인터럽트통신회로는 래치와 JK-플립플롭 및 버퍼를 이용하여 지능모듈간의 1대 N의 다중인터럽트통신이 가능하도록 구성된다.The present invention relates to a multi-interrupt communication circuit. The multi-interrupt communication circuit of the present invention is configured to enable 1-to-N multi-interrupt communication between intelligent modules using a latch, a JK-flip-flop, and a buffer.

따라서, 본 발명은 1개의 인터럽트입력으로 복수의 인터럽트통신을 구현하며, 1개의 인터럽트입력으로 연결 할 수 있는 전송모듈의 제한이 없다. 또한, 래치 및 플립플롭을 이용하므로 저렴한 비용으로 간단하게 1대 N의 인터럽트통신을 구현하며, 인터럽트인식기능이 자동적으로 실현되어 추가적인 스프트웨어나 하드웨어적 고려가 필요없다.Therefore, the present invention implements a plurality of interrupt communications with one interrupt input, and there is no limitation of a transmission module that can be connected with one interrupt input. In addition, latch and flip-flop are used to implement simple one-to-n interrupt communication at low cost, and the interrupt recognition function is automatically realized so that no additional software or hardware considerations are required.

Description

다중인터럽트통신회로Multi Interrupt Communication Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 바람직한 실시예에 따른 다중인터럽트통신회로를 나타내는 블록도.1 is a block diagram showing a multi-interrupt communication circuit according to a preferred embodiment of the present invention.

Claims (7)

하나의 외부인터럽트입력단자를 구비한 마이콤과 인터럽트통신을 하는 복수개의 지능모듈에 있어서, 마이콤에 의해 각 구성요소들의 동작을 제어하도록 설계된 제어부; 상기 지능모듈에 대응하게 연결되며, 지능모듈에서 처리된 데이타를 저장했다가 제어부의 출력인에이블신호에 따라 출력되는 복수개의 래치; 상기 지능모듈에 대응하게 연결되며, 지능모듈에서 인터럽트가 발생하면 출력값을 일정상태로 하여 상기 마이콤에 인터럽트를 발생한 지능모듈을 알려주기 위한 복수개의 인터럽트인지수단; 및 상기 지능모듈로부터 인터럽트가 걸리면 외부 인터럽트를 마스크하고 인터럽트서비스루틴으로 분기하여 상기 인터럽트인지수단에 의해 인지된 인터럽트를 발생한 지능모듈에 연결된 래치로부터 저장된 데이타를 읽어들이는 마이콤을 포함하는 다중인터럽트통신회로.A plurality of intelligent modules for interrupt communication with a microcomputer having one external interrupt input terminal, the intelligent module comprising: a control unit designed to control operation of each component by the microcomputer; A plurality of latches corresponding to the intelligent module and configured to store data processed by the intelligent module and to be output according to an output enable signal of the controller; A plurality of interrupt recognition means connected to the intelligent module to inform the micom of the intelligent module that caused the interrupt by outputting a predetermined state when an interrupt occurs in the intelligent module; And a microcomputer for masking an external interrupt when the interrupt is received from the intelligent module, branching to an interrupt service routine, and reading the stored data from a latch connected to the intelligent module which generated the interrupt recognized by the interrupt acknowledgment means. . 제1항에 있어서, 상기 인터럽트인지수단은 상기 제어부의 출력인에이블신호에 클럭단자로 인가받아 출력값의 상태를 토글시키고, 세트상태에서 대응하는 지능모듈로 부터 인터럽트가 발생하면 출력값의 상태를 반전시키는 JK-플립플롭으로 이루어진 것을 특징으로 하는 다중인터럽트통신회로.The method according to claim 1, wherein the interrupt acknowledgment means is applied to the output enable signal of the control unit as a clock terminal to toggle the state of the output value, and inverts the state of the output value when an interrupt occurs from the corresponding intelligent module in the set state. Multi-interrupt communication circuit, characterized in that consisting of JK-flip-flop. 제2항에 있어서, 상기 JK-플립플롭의 출력단에 연결되며 각각의 JK-플립플롭의 출력값을 저장하고, 제어부의 출력인에이블신호에 따라 저장내용을 마이콤에 전달하는 버퍼를 더 포함하는 다중인터럽트통신회로.3. The multi-interrupt of claim 2, further comprising a buffer connected to an output terminal of the JK flip-flop and configured to store an output value of each JK flip-flop, and to transfer the stored contents to the microcomputer according to the output enable signal of the controller. Communication circuits. 제3항에 있어서, 상기 마이콤은 상기 버퍼로 부터 인가되는 데이타중 정해진 상태를 갖는 비트자리에의해 인터럽트를 발생한 지능모듈을 인식하는 것을 특징으로 하는 다중인터럽트통신회로.4. The multi-interrupt communication circuit according to claim 3, wherein the microcomputer recognizes the intelligent module which generated the interrupt by the bit position having a predetermined state among the data applied from the buffer. 제4항에 있어서, 상기 래치와 JK-플립플롭은 지능모듈의 갯수가 늘어남에 따라 더 추가하여 설치하도록 한 것을 특징으로 하는 다중인터럽트통신회로.5. The multi-interrupt communication circuit according to claim 4, wherein the latch and the JK-flip-flop are further installed as the number of intelligent modules increases. 제3항에 있어서, 상기 지능모듈은 대응하는 JK-플립플롭의 출력값에 따라 상기 마이콤이 래치로부터 데이타를 읽어가는 상태를 인식하는 것을 특징으로 하는 다중인터럽트통신회로.4. The multi-interrupt communication circuit according to claim 3, wherein the intelligent module recognizes the state in which the microcomputer reads data from the latch according to the output value of the corresponding JK flip-flop. 제4항에 있어서, 상기 마이콤은 상기 버퍼의 데이타중 정해진 상태를 갖는 비트자리가 복수개 이상이면 정해진 우선순위에 따라 래치들의 저장내용을 읽어들이는 것을 특징으로 하는 다중인터럽트통신회로.5. The multi-interrupt communication circuit according to claim 4, wherein the microcomputer reads the stored contents of the latches according to a predetermined priority when there are a plurality of bit positions having a predetermined state among the data of the buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940015573A 1994-06-30 1994-06-30 Multiple interrupt communication circuit KR100244885B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940015573A KR100244885B1 (en) 1994-06-30 1994-06-30 Multiple interrupt communication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940015573A KR100244885B1 (en) 1994-06-30 1994-06-30 Multiple interrupt communication circuit

Publications (2)

Publication Number Publication Date
KR960002030A true KR960002030A (en) 1996-01-26
KR100244885B1 KR100244885B1 (en) 2000-02-15

Family

ID=19386953

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940015573A KR100244885B1 (en) 1994-06-30 1994-06-30 Multiple interrupt communication circuit

Country Status (1)

Country Link
KR (1) KR100244885B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381403B1 (en) * 1995-06-23 2003-07-18 칼소닉 칸세이 가부시끼가이샤 Microcomputer wake-up device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60168240A (en) * 1984-02-10 1985-08-31 Nec Corp Interrupt processing circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100381403B1 (en) * 1995-06-23 2003-07-18 칼소닉 칸세이 가부시끼가이샤 Microcomputer wake-up device

Also Published As

Publication number Publication date
KR100244885B1 (en) 2000-02-15

Similar Documents

Publication Publication Date Title
KR850008017A (en) CMOS input / output circuit
KR880010365A (en) Bus Interface Circuits for Digital Data Processors
KR970049625A (en) Peripheral Selection System
KR960042413A (en) Data processing system
KR950704757A (en) IC card reader / writer and control method
KR960002030A (en) Multi Interrupt Communication Circuit
RU2066066C1 (en) Serial-parallel interface device
KR970007157Y1 (en) Interface apparatus between system bus and multiple parallel port
KR100292622B1 (en) Semiconductor memory device and method for coding signal of the same
KR960001268B1 (en) Data control apparatus between buses with a flag mode
KR100217738B1 (en) Computer communication speed improving method of keyphone
KR900005661B1 (en) Data transmitting circuit and mehtod between controller and laser printer
KR0168010B1 (en) One point control method and circuit in dual frequency send of an exchanger
KR0127884B1 (en) Mail box interrupt generating device
KR900005907Y1 (en) Circuit for expanding data transfer rate of computer terminal
KR0134119Y1 (en) Data interface circuit of one-chip microcomputer and main computer system
SU1410045A1 (en) Exchange channel
KR980007357A (en) Matching Device Transmitter in Electronic Switching System
KR960016307A (en) Device and method for connecting digital key phone in digital key phone system
KR900015491A (en) Interface circuit for data communication
KR950020167A (en) Switching device from PCI card to ISA card
KR970049313A (en) Interface device of device having control board and operation panel board
KR910010325A (en) Data transmission system using personal computer
KR960020102A (en) Multiple Serial Interfaces for Wireless Public Telephones
JPS63103531A (en) Relay control system for digital signal

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20031124

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee