KR960000841B1 - Digital level detection circuit - Google Patents

Abstract

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Description

Digital level detection circuit

1 and 3 are schematic diagrams of an example of the present invention.

2 and 4 to 8 are diagrams for explaining the same.

* Explanation of symbols for main parts of the drawings

12: detection circuit 15,22: ROM

The present invention relates to a digital level detection circuit.

According to the present invention, in the digital level detection circuit, the hold time of the hold time when the level of the input signal is decreased is made zero, so that the variation in the hold time is reduced.

In an audio signal system such as an 8 mm video or an electronic still camera, the audio signal level is recorded with a predetermined characteristic at the time of recording, and the level of the reproduced video signal at the time of reproduction is complementary to that at the time of recording. To get the original audio signal.

In 8 millisecond video, an audio signal is recorded by changing a PCM signal, and in an electronic still camera, the audio signal is converted from an analog signal to a digital signal at the time of recording to perform time-base compression.

Therein, the same thing as that shown in Fig. 4 is considered as the level compression circuit of the audio signal.

That is, in the same figure, the analog audio signal Sa is supplied to the operational amplifier 2 through the input terminal 1, and the variable attenuator (multiplication circuit) (in the negative feedback path of the operational amplifier 2) ( 3) is connected. Therefore, by controlling the amount of attenuation of the attenuator 3, the level compressed audio signal Sc is drawn out from the amplifier 2.

Thus, this signal Sc is supplied to the A / D converter 4, converted into a digital signal Sd having a predetermined number of bits, and the signal Sd is drawn out to the output terminal 5. At this time, the signal Sd is supplied to the digital level detection circuit 6 so that the detection signal V (t) of the level at which the signal Sd is shown (the level of the analog signal when the signal Sd is converted into an analog signal) is digital. It is drawn out in the state of a signal, and this signal V (t) is supplied to the attenuator 3 as a control signal.

Therefore, the signal Sd of the terminal 5 is a digital signal in which the audio signal Sa is level compressed and A / D converted.

In this case, the attack response characteristic, the hold response characteristic and the recovery response characteristic with respect to the signal Sd are as shown in FIG. However, the same figure shows and converts these response characteristics into an analog signal.

Thus, FIG. 5A shows the attack response characteristic, and when the level of the signal Sd rises stepwise from the value a to the value b at time t = 0, the attack response characteristic of the signal (voltage) V (t) is

V (t) = ((b ^N -a ^N ) (1-exp (t / L)) + a ^N ) ^{N / N} ... … … … … … … … … … … … (i)

N and T are represented by integers. 5B shows the hold response characteristic and the responsive response characteristic, and when the level of the signal Sd drops gradually to the value b at the time point t = 0, the hold response characteristic of the signal V (t) is a period of t ≦ tH. about,

V (t) = a... … … … … … … … … … … … … … … … … … … … … … … … … … (Ii)

And the response response characteristic for t≥tH

V (t) = ((ba) exp (-(t-tH / T _K ) ÷ a …………………………………… (ⅲ)

T _H · T _R is represented by an integer.

In addition, having such a hold response characteristic and a responsive response characteristic means that when the frequency of the signal Sa is low, the ripple component of the signal V (t) increases and the signal St is modulated, and as a result, local distortion increases. To prevent that.

Therefore, as is also apparent in FIG. 5A, in the attack response characteristic, the voltage Vi (= V (i)) at any time t = i is one sampling point t = i-1 before the time point t = i. The difference ΔV may be added to the voltage Vi-1 (= V (i-1)), and the difference ΔV is an integer for the attack response determined by the ratio of the voltage Vi-1 and the absolute value | Sd | of the signal Sd. Obtained on the basis of Therefore, when the difference of each sampling period is sequentially added to the value a, the voltage V (t) at that time t is obtained. In addition, the hold response characteristic is flat as indicated by the equation (ii), and the restoration response characteristic is the same as the discharge curve (exponential irrigation characteristic) of the capacitor, as indicated by the expression (iii). Discrete ignition formula, (ⅲ) formula,

V (t) = (| Sd | -V (t-1)) K + a)... … … … … … … … … … … … … … … … (Ⅳ)

It becomes That is, the voltage V (t) has a constant value K as the difference between the voltage | Sd | at the present time t = i and the voltage Vi-1 at the previous sampling time point t = i-1 with the value a as an initial value. By multiplying the multiplication by the value a, it can be found.

Therefore, the detection circuit 6 having the above response characteristics can be configured as shown in FIG.

That is, in FIG. 6, the digital signal Sd is supplied to the absolute value detecting circuit 12 through the input terminal 11, and at this time t = i, the digital Sd is connected to the absolute value through the input terminal 11. The signal | Sd | is supplied to the detection circuit 12 to represent the absolute value | Sd | of the signal Sd at the present time t = i, and this signal | Sd | is supplied to the divider circuit 13 and described later. The signal Vi-1 (= V (i-1)) is supplied to the divider circuit 13 at the sampling time point t = i-1 one earlier than the present time t = i in the latch 18. The division circuit 13 realizes division of Vi-1 / | Sd | by repeating the subtraction of (Vi-1- | Sd |) and the bit shift of the signal Vi-1. Therefore, when the first subtraction (Vi-1- | Sd |) is subtracted in the first division, as is apparent from FIG. 5,

Upon attack response… Vi-1- | Sd | <0

Upon restoration response… Vi-1- | Sd | ≥0

(When hold response)

Of (Vi-1- | Sd |) after the first subtraction

In response to attack… "One"

In response to a restore… "0"

(When hold response)

It becomes There, this MSB is supplied as a control signal to the switch circuit 32 via the latch 31.

Therefore, in the attack response, the division signal Vi-1 / | Sd | in the division circuit 13 is supplied to the address signal forming circuit 14, and the address signal corresponding to each time point at the ratio Vi-1 / | Sd | Is formed, the address signal is supplied to the ROM 15, and the value (coefficient) K ₀ obtained by quantifying the difference ΔV (= Vi-Vi-1) at each time point is extracted, and this value K ₀ is a multiplication circuit. While supplying to (16), the signal | Sd | is supplied to the multiplication circuit 16 from the detection circuit 12, and the value K ₀ is multiplied by the signal | Sd |, so that the difference? The supply circuit 17 is supplied to the addition circuit 17 via 32, and the signal Vi-1 is formed at the latch 18. The signal Vi-1 is drawn out to the output terminal 19 via the latch 18. This signal Vi has the attack response characteristic shown in FIG. 5A.

On the other hand, in the hold response and the recovery response, as described above, the division circuit 13 outputs an MSB of &quot; 0 &quot;, but this MSB is a retriggerable counter for a timer via the latch 31) (2 ) Is supplied as a clear and start signal (count enable signal) of the counter so that the counter 21 is supplied with a count of a clock (not shown) as a count value enable signal) at a time point t = 0, so that the counter 21 Output is supplied to the ROM 22 as an address signal, a value of 0 is extracted from the ROM 22 in a count value t &lt; tH, and a constant value K is extracted as a recovery coefficient in a period of t &gt; tH. In the period t, tH, a constant value K is taken out as a recovery coefficient, and this value 0 or K is supplied to the multiplication circuit.

Again, the signal | Sd | in the detection circuit 12 is supplied to the subtraction circuit 24, and at the same time, the signal Vi-1 from the latch 18 is supplied to the subtraction circuit 24, and the difference ΔV (= | Sd | -Vi-1) is taken out, and this difference [Delta] V is supplied to the multiplication circuit 23 and multiplied by the value 0 or K. In this case, the difference ΔV is for every constant sampling period as shown in Fig. 5b, and the reconstruction response characteristic is obtained by adding the value a to a simple exponential irrigation characteristic as shown in the equation (i). The multiplication output of ΔV and a value of 0 or K shows the decrease (change) of the signal V (t) in the hold response (t ≦ tH) or the restore response (t ≦ tH).

Therefore, at this time, since the switch circuit 32 is switched to the state opposite to the figure, the multiplication output of the multiplication circuit 23 is supplied to the addition circuit 17 via the switch circuit 32. Therefore, from the addition circuit 17, a signal Vi having the hold response characteristic and the recovery response characteristic shown in FIG. 5B is obtained, which is drawn out to the terminal 19. As shown in FIG.

In this way, according to this detection circuit, it is possible to obtain the detection signal V (t) having the attack response characteristic, the hold response characteristic and the restoration response characteristic shown in formulas (i) to (iii) (document: Japanese Patent Application Digestion No. 60-57215 specification and drawings)

The hold response characteristic described above is expressed in the formula (ii) in the period of 0 ≦ t ≦ tH,

V (t) = a

And the level at time t = 0 is completely held, which is an ideal hold response characteristic.

In reality, however, the signal Sd is discrete in time, which may cause an error in the signal V (t).

That is, FIG. 7 shows the signals Sd and V (t) converted to analog signals. Therefore, if the signal Sd is changed as shown by the broken line when the signal is temporally continuous, the actual signal Sd which is discrete in time is obtained for each sampling, so it is distributed so as to be shown in the same figure in the same drawing. do.

Therefore, if the signal Sd at a point in time t = t1 is the data sampled at the peak value, the signal Sd is at the last maximum at this point in time t1, since the signal Sd is not in synchronism with the sampling frequency. Sd is smaller than the signal Sd at the time point t1.

Therefore, in the above-described detection circuit 6, the signal V (t) changes as shown by the X table, that is, Vi-1 &gt; | Sd | at the time point t1. The MSB of becomes "0" at time t1. Therefore, when the signal V (t) is held at the time point t = t1 and reaches the time point ts after the period tH at the time point t1, the recovery response operation is entered.

Therefore, since the time point t1 at which the signal Sd becomes the sampled peak value changes in balance with the sampling of the signal Sd, the position of the period tH of the hold response also changes, and as a result, the hold response (for example, the time point t =). The period from 0 to the time when the level of the signal V (t) decreases by 2 dB is the minimum is almost 0 (when the time t = 0 coincides with the time t3) and the maximum is the set value tH (the time t = 0 and the time t1 Largely unbalanced).

In addition, for example, in 8 millisecond video, it is assumed that the level compression and the control signal V (t) are formed by analog processing, so that the signal V (t) changes as shown by the solid line in FIG. However, in the detection circuit 6 described above, the signal V (t) is changed as shown by the broken line, and the secondary (diagonal portion) becomes a hearing problem.

The present invention is intended to solve the above problems.

For this reason, in the present invention, the coefficient 0 of the hold response characteristic and the coefficient K of the responsive response characteristic written in the ROM 22 are set to K1 and K2 (K1 and K2 are predetermined values other than 0, respectively).

The level of the signal V (t) changes as shown in FIG. 2, so that the hold timing is unbalanced.

The method of claim 1 also, ROM (22), the value K1 is written as a function of the hold teugeong response, as a function of restored response, the value K ₂ is written.

only,

K ₁ <0, K ₂ <0 (K ₂ = K)

| K ₁ | <| K ₂ |

It becomes

According to such a configuration, when the signal Sd changes as shown in FIG. 2 (FIG. 2 is the same as FIG. 7 with respect to the signal Sd), the hold response operation is also started at time t ₁ . Since the output of the ROM 22 becomes the value K ₁ (≠ 0), assuming that the signal V (t) is continuous in time, the signal V (t) is equal to the value K ₁ as shown by a thin line in the same figure. Correspondingly, it descends slowly (X mark represents the actual discrete signal V (t)).

Therefore, at the subsequent sampling time points t ₂ and t ₃ after the time point t ₁ , Vi-1 ≧ Vi 1 is the absolute value of the signal Sd at the time points t ₂ and t ₃ , and is equivalent to that indicated by a table in the same figure. The hold response operation is performed at the time points t ₂ and T ₃ , respectively.

However, at the next sampling time point t ₄ , Vi-1 <| Sd | Therefore, the attack response operation is performed at this time t ₄ , and the signal V (t) rises (thin line).

Therefore, since the same operation as that at this time point t ₂ , t ₃ , t ₄ is performed for each sampling time point, the signal V (t) is represented by the x table.

Thus, at the time ts, Vi-≥ | is in, attack the response operation is performed at the same time the load, after that, Vi-1 <| | Sd Sd | because it becomes a hold-response operation at this time t5, the test at t ₅ It is a hold response characteristic over time period tH, and it becomes a restoration response characteristic after that.

In addition, even during the period tH of the hold response characteristic, the signal V (t) gradually decreases in response to the value K ₁ . Thus, as shown in Fig. 8, the hold response characteristic when the step input is supplied is

V (t) = ((ba) exp (−t) T _H ) + a... … … … … … … … … … … … (Ⅴ)

Indicated by the restore response attribute,

V (t) = (bv (tH)) exp (− (t-tH / T _R ) + V (tH) ……………… (Vi)

The discharge curve (exponent irrigation characteristic) of the capacitor is expressed by these (V) and (Vi) formulas. In the formula (Vi), if V (tH) = a, the formula (Vi) corresponds to the formula (ⅲ).

In this way, in the present invention, since the level of the signal V (t) is also lowered in the hold response operation, as shown in FIG. 2, the hold response operation close to the original correct hold response operation is performed. That is, the point in time t ₄ of the last Vi-1 &lt; | Sd | may not deviate from the immediately preceding half cycle period at time point t = 0, as shown in FIG. 2, and thus the operation period tH of the hold response. Although the position of is also shifted back and forth, since the sampling period is an order of mu sec, the operation period tH of the hold response is an order of m seconds, so the deviation of the position of the operation period tH of the hold response is sufficiently small. In particular, when | K ₁ | is made larger, the deviation of the position of the operation period tH becomes further smaller. By the way, in the case of 8mm video,

tH = 5.4 m sec

Sampling period = 15.9 μs (4x oversampling)

K ₁ = -3.66 × 10 ^-5

K ₃ = -3.66 × 10 ^-4

You can do

In addition, since the signal V (t) falls even during the operation period tH of the hold response, the difference (the oblique portion in FIG. 8) from the case of analog processing is reduced, and the auditory characteristic is improved.

In the example shown in FIG. 3, in the operation of the attack response, a predetermined attack characteristic is obtained by multiplying the difference ΔV by the coefficient K0 and adding them sequentially.

As described above, the value K ₁ may be changed with time in the hold response to coincide with or approximate the characteristics of the analog processing shown in FIG. The present invention also applies to the level detecting circuit of the level expanding circuit.

According to the present invention, even during the hold response operation, the level of the signal V (t) is lowered. Therefore, as is apparent from FIG. 2, the hold response operation close to the original accurate hold response operation is performed. In addition, since the signal V (t) falls even during the operation period tH of the hold response, the difference from the case of the analog processing is small, and the auditory characteristic is improved.

Claims (1)

A detection circuit for detecting the absolute value of the input digital data, a division circuit for calculating the ratio between the absolute value and the level detection output, a first memory storing an integer for the attack response, a hold response and a restoration response And a second memory having a constant stored therein, and an arithmetic circuit, wherein the constant for the attack response is a value that changes with time in the attack response, and the constant for the hold response and the restore response is 0. Is a value other than 0, and the attack response operation, the hold response operation, and the restoration response operation are switched based on the output of the division circuit, so that the multiplication and addition are performed between the constant for the attack response and the level detection output to perform the input. The level detection output, which shows the level of the digital data, is drawn out, and in the hold response operation and the recovery response operation, And a multiplication and addition are performed between the constant for the hold response and the restore response and the level detection output so that the level detection output showing the level of the input digital data is extracted.

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