KR950035108A

KR950035108A - Encoding device

Info

Publication number: KR950035108A
Application number: KR1019940010794A
Authority: KR
Inventors: 윤성욱
Original assignee: 배순훈; 대우전자 주식회사
Priority date: 1994-05-17
Filing date: 1994-05-17
Publication date: 1995-12-30

Abstract

본 발명은 하드웨어적인 구성이 간단하게 되도록 하기에 적합한 계층 부호화 장치에 관한 것으로, 종래에는 제1도의 감산기(1)가 원래의 영상 신호와 영산 신호가 부호화된 역 이산 코사인 변환부(5)의 영산 신호의 차이 신호를 구하는 방식으로 계층 부호화를 실시함으로써 실제적으로 두 개의 계층이 나오는데에 걸리는 시간 차가 한 프레임에 따른 시간이 걸리며, 전체 부호화 장치가 하드웨어적으로 복잡해 지는 결점이 있었으나, 본 발명에서는 제1 양자화부(21)의 양자화된 영상 신호 중에서 나머지에 따른 신호를 제2 양자화부(25)에 의해서 다시 한번 양자화하여 결국, 제1, 제2 양자화부(21,25)의 각 몫에 따른 신호를 부호화하여 제1, 제2 역 양자화부(24,28)에 의해 최종적으로 출력되는 신호를 가산함으로써 종래와 같은 피드팩이 필요없기 때문에 전체 구성이 하드웨어적으로 간단하면서도 시간적인 지연없이 부호화를 실현할 수 있으므로 상기 결점을 개선시킬 수 있는 것이다.The present invention relates to a hierarchical encoding device suitable for simplifying a hardware configuration. In the related art, a subtractor 1 of FIG. 1 performs the operation of an inverse discrete cosine transform unit 5 in which an original video signal and a product signal are encoded. Although the difference in time between two layers actually takes time according to one frame by performing hierarchical encoding by a method of obtaining a difference signal of a signal, there is a drawback that the entire encoding apparatus is hardware-complicated. The second quantizer 25 quantizes the signal corresponding to the rest of the quantized image signals of the quantizer 21 by using the second quantizer 25 and finally generates a signal corresponding to each quotient of the first and second quantizers 21 and 25. By adding the signals finally outputted by the first and second inverse quantizers 24 and 28 by encoding, the feed pack as in the prior art is not necessary. Because this property can be realized, while the encoding hardware simple with no time delay is to improve the above drawbacks.

Description

Encoding device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 계층 부호화의 일 실시예를 나타낸 블럭도.2 is a block diagram illustrating an embodiment of hierarchical coding according to the present invention.

Claims

A first quantization unit 21 for quantizing the video signal; A first variable length encoder 22 for variable length encoding the signal according to the quotient among the signals of the first quantizer 21; A first inverse variable length encoder (23) for inversely variable length coding the signal of the first variable length encoder (22); A first inverse quantizer (24) for inversely quantizing the signal of the first inverse variable length encoder (23); A second quantization unit 25 for quantizing a signal according to the rest of the signals of the first quantization unit 21; A second variable length encoder 26 for variable length coding the signal according to the quotient among the signals of the second quantizer 25; A second inverse variable length encoder 27 for inversely variable length encoding the signal of the second variable length encoder 26; A second inverse quantizer (28) for inversely quantizing the signal of the second inverse variable length encoder (27); And an adder (29) for adding the signal of the second inverse quantizer (28) and the signal of the first inverse quantizer (25).

※ Note: The disclosure is based on the initial application.