KR950034839A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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KR950034839A
KR950034839A KR1019950012652A KR19950012652A KR950034839A KR 950034839 A KR950034839 A KR 950034839A KR 1019950012652 A KR1019950012652 A KR 1019950012652A KR 19950012652 A KR19950012652 A KR 19950012652A KR 950034839 A KR950034839 A KR 950034839A
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semiconductor
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intrinsic
silicon
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사토시 데라모토
히사시 오타니
야스히코 다케무라
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야마자끼 순페이
가부시키가이샤 한도오따이 에네루기 겐큐쇼
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Abstract

반도체 장치, 특히 스태거형 박막트랜지스터는 N형 또는 P형 불순물을 함유한 한쌍의 반도체 영역; 반도체 영역 위, 또는 아래 제공되고, 반도체 영역과 실제 동일한 모양을 가는 비정질 실리콘의 결정화를 가속하는 촉매원소를 함유한 층; 반도체 영역을 덮기 위해 제공된 실제 지성인 반도체 층; 반도체 층을 덮는 절연막; 및 절연막상에 제공된 게이트 전극을 포함한다. 또한 상기 반도체 장치의 제조공정이 청구된다.Semiconductor devices, particularly staggered thin film transistors, include a pair of semiconductor regions containing N-type or P-type impurities; A layer provided above or below the semiconductor region, the catalyst containing a catalyst element for accelerating crystallization of amorphous silicon having a substantially same shape as the semiconductor region; An actual oily semiconductor layer provided to cover the semiconductor region; An insulating film covering the semiconductor layer; And a gate electrode provided on the insulating film. In addition, a manufacturing process of the semiconductor device is claimed.

Description

반도체 장치 및 그 제조방법Semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 내지 제1D도는 본 발명의 한 실시예(실시예1)에 따른 공정의 단계를 위한 횡단면을 보여주는 다이아그램.1A-1D are diagrams showing cross-sections for steps in a process according to one embodiment of the present invention (Example 1).

Claims (24)

실리콘을 포함하고 불순물 전도성 형태를 갖는 한쌍의 반도체 영역; 상기 반도체 영역 위 또는 아래에 제공되며, 실리콘의 결정화를 가속시키는 촉매원소를 함유하고 상기 반도체 영역과 실제로 공동연장하는 층; 상기 반도체 영역상에 형성되고 그 영역사이에 연장하며, 실리콘을 포함하는 실제 진성인 반도체 층; 상기 반도체층상에 형성된 절연막; 및 절연막상 제공된 게이트 전극을 포함하는 반도체 장치.A pair of semiconductor regions comprising silicon and having an impurity conductive form; A layer provided above or below the semiconductor region and containing a catalytic element for accelerating crystallization of silicon and actually coextending with the semiconductor region; An intrinsic intrinsic semiconductor layer formed on and extending between said semiconductor regions, said silicon comprising silicon; An insulating film formed on the semiconductor layer; And a gate electrode provided on the insulating film. 제1항에 있어서, 불순물 전도성 형태를 갖는 상기 반도체 영역은 소오스 및 드레인 영역으로서 기능하고 상기 실제 진성인 반도체층은 채널영역으로서 기능하는 반도체 장치.2. The semiconductor device of claim 1, wherein the semiconductor region having an impurity conductive form functions as a source and drain region and the actual intrinsic semiconductor layer functions as a channel region. 제1항에 있어서, 두 상기 반도체 영역과 상기 실제 진성인 반도체층이 결정성 실리콘을 포함하는 반도체 장치.2. The semiconductor device of claim 1, wherein the two semiconductor regions and the actual intrinsic semiconductor layer comprise crystalline silicon. 실리콘을 포함하고 불순물 전도성 형태를 갖는 한쌍의 반도체 영역; 상기 반도체 영역상 형성되고 그 영역사이에 연장하며, 실리콘을 포함하는 실제 진성인 반도체층; 상기 반도체층상에 형성되 절연막; 및 절연막상에 제공된 게이트 전극을 포함하고, 상기 게이트 전극 아래에 위치된 상기 반도체층의 적어도 일부분이 1×1016내지 1×1019원자/㎤의 농도에서 실리콘의 결정화를 촉진시킬 수 있는 촉매원소를 함유하는 반도체 장치.A pair of semiconductor regions comprising silicon and having an impurity conductive form; An intrinsic intrinsic semiconductor layer formed over said semiconductor region and extending between said regions; An insulating film formed on the semiconductor layer; And a gate electrode provided on the insulating film, wherein at least a portion of the semiconductor layer positioned below the gate electrode is capable of promoting crystallization of silicon at a concentration of 1 × 10 16 to 1 × 10 19 atoms / cm 3. A semiconductor device containing the. 제4항에 있어서, 상기 촉매원소가 니켈(Ni), 철(Fe), 코발트(Co), 루테늄(Ru), 뢰듐(Rh), 팔라듐(Pb), 오스뮴(Os), 이리듐(Ir), 백금(Pt), 스칸듐(Sc), 바나듐(V), 망간(Mn), 구리(Cu), 아연(Zn), 금(Au), 및 은(Ag)으로 구성된 그룹으로부터 선택되는 반도체 장치.The method of claim 4, wherein the catalytic element is nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pb), osmium (Os), iridium (Ir), A semiconductor device selected from the group consisting of platinum (Pt), scandium (Sc), vanadium (V), manganese (Mn), copper (Cu), zinc (Zn), gold (Au), and silver (Ag). 실리콘을 포함하고 불순물 전도성 형태를 갖는 한쌍의 반도체 영역; 상기 반도체 영역상에 형성되고 그 영역사이에 연장하며, 실리콘을 포함하는 실제 진성인 반도체 층; 절연막상에 제공된 게이트 전극을 포함하고, 상기 한쌍의 반도체 영역사이에 연장하는 상기 반도체층의 일부분이 상기 반도체 영역과 같은 방향으로 결정화되는 반도체 장치.A pair of semiconductor regions comprising silicon and having an impurity conductive form; An intrinsic intrinsic semiconductor layer formed on and extending between said semiconductor regions, said silicon comprising silicon; And a gate electrode provided on the insulating film, wherein a portion of the semiconductor layer extending between the pair of semiconductor regions is crystallized in the same direction as the semiconductor region. 제6항에 있어서, 불순물 전도성 형태를 갖는 상기 반도체영역은 소오스 및 드레인 영역으로서 기능하고 상기 실제 진성인 반도체 층은 채널 영역으로서 기능하는 반도체 장치.7. The semiconductor device of claim 6, wherein the semiconductor region having an impurity conductive form functions as a source and drain region and the actual intrinsic semiconductor layer functions as a channel region. 절연표면을 갖픈 기판; 결정성 실리콘을 포함하고 상기 기판위에 형성된 한쌍의 호오스 및 드레인 반도체층; 및 상기 소오스 및 드레인 반도체층 사이에 연장하고 결정성 실리콘을 포함하는 채널 반도체 층을 포함하고, 각각의 상기 소오스 및 드레인 반도체층과 상기 채널 반도체층이 결정화공정 동안 상기층의 결정화를 촉진 시킬 수 있는 촉매원소를 함유하는 반도체 장치.A substrate having an insulating surface; A pair of hose and drain semiconductor layers comprising crystalline silicon and formed on said substrate; And a channel semiconductor layer extending between the source and drain semiconductor layers and comprising crystalline silicon, wherein each of the source and drain semiconductor layers and the channel semiconductor layer are capable of promoting crystallization of the layer during the crystallization process. A semiconductor device containing a catalytic element. 제8항에 있어서, 상기 촉매원소가 1×1019㎤ 이하의 농도로 상기 층에 함유되는 반도체 장치.The semiconductor device according to claim 8, wherein the catalyst element is contained in the layer at a concentration of 1 × 10 19 cm 3 or less. 제8항에 있어서, 상기 소오스 및 드레인 영역과 접촉하게 형성된 한쌍의 금속층을 추가로 포함하는 반도체 장치.The semiconductor device of claim 8, further comprising a pair of metal layers formed in contact with the source and drain regions. 실리콘의 결정화를 촉진시킬 수 있는 촉매원소를 함유한 층을 기판위에 형성하는 단계; 상기 층과 접촉하게 N-형 또는 P-형 비정질 실리콘 막을 형성하는 단계; 상기 N형 또는 P형 비정질 실리콘막을 에칭하여 소오스 및 드레인 영역으로서 한쌍의 반도체 영역을 형성하는 단계; 상기 한쌍의 반도체 영역상에 진성 비정질 실리콘막을 형성하는 단계; 상기 진성 비정질 실리콘을 상기 촉매원소의 원조에 의해 가열함으로써 결정화시키는 단계를 포함하는 반도체 장치의 제조방법.Forming on the substrate a layer containing a catalytic element capable of promoting crystallization of silicon; Forming an N-type or P-type amorphous silicon film in contact with the layer; Etching the N-type or P-type amorphous silicon film to form a pair of semiconductor regions as source and drain regions; Forming an intrinsic amorphous silicon film on the pair of semiconductor regions; And crystallizing the intrinsic amorphous silicon by heating with the aid of the catalytic element. 제11항에 있어서, 상기 가열후에 상기 실리콘막 상에 레이저로서 레이저 방사 또는 동등한 세기의 강한광을 조사하는 단계를 추가로 포함하는 반도체 장치의 제조방법.12. The manufacturing method of a semiconductor device according to claim 11, further comprising irradiating laser radiation or strong light of an equal intensity on the silicon film after the heating with a laser. 제11항에 있어서, 상기 촉매원소 함유층이 스핀코팅에 의해 형성되는 반도체 장치의 제조방법.12. The method of claim 11, wherein the catalyst element-containing layer is formed by spin coating. 제11항에 있어서, 상기 촉매원소 함유층이 스퍼터링에 의해 형성되는 반도체 장치의 제조방법.The manufacturing method of a semiconductor device according to claim 11, wherein said catalyst element-containing layer is formed by sputtering. 제11항에 있어서, 상기 기판이 유리기판인 반도체 장치의 제조방법.The method of claim 11, wherein the substrate is a glass substrate. 제11항에 있어서, 상기 결정화 전에 상기 실리콘막상에 절연막을 형성하는 단계를 추가로 포함하는 반도체 장치의 제조방법.12. The method of claim 11, further comprising forming an insulating film on the silicon film before the crystallization. 제16항에 있어서, 상기 절연막과 상기 실피콘막을 에칭하여 상기 소오스 및 드레인 영역을 위한 콘택트홀을 형성하는 단계; 및 상기 절연막상에 게이트 전극을 형성하는 단계를 추가로 포함하는 반도체 장치의 제조방법.17. The method of claim 16, further comprising: etching the insulating film and the silicon cone film to form contact holes for the source and drain regions; And forming a gate electrode on the insulating film. 제11항에 있어서, 상기 결정화 후에 상기 실리콘막상에 절연막을 형성하는 단계를 추가로 포함하는 반도체 장치의 제조방법.12. The method of claim 11, further comprising forming an insulating film on the silicon film after the crystallization. 제18항에 있어서, 상기 절연막과 상기 실리콘막을 에칭하여 상기 소오스 및 드레인 영역을 위한 콘택트홀을 형성하는 단계를 추가로 포함하는 반도체 장치의 제조방법.19. The method of claim 18, further comprising etching the insulating film and the silicon film to form contact holes for the source and drain regions. 제16항에 있어서, 상기 층이 상기 N형 또는 P형 비정질 실리콘막이 아래에 형성되는 반도체 장치의 제조방법.17. The method of claim 16, wherein the layer is formed under the N-type or P-type amorphous silicon film. 제16항에 있어서, 상기 층이 상기 N형 또는 P형 비정질 실리콘막이 위에 형성되는 반도체 장치의 제조방법.17. The method of claim 16, wherein the layer is formed on the N-type or P-type amorphous silicon film. 제18항에 있어서, 상기 층이 상기 N형 또는 P형 비정질 실리콘막이 아래에 형성되는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 18, wherein said layer is formed below said N-type or P-type amorphous silicon film. 제18항에 있어서, 상기 층이 상기 N형 또는 P형 비정질 실리콘막이 위에 형성되는 반도체 장치의 제조방법.19. The method of claim 18, wherein the layer is formed on the N-type or P-type amorphous silicon film. N형 또는 P형 비정질 실리콘막을 형성하는 제1단계; N형 또는 P형 비정질 실리콘막을 에칭하여, 소오스/드레인 영역을 제공하는 한쌍의 반도체 영역을 형성하는 제2단계; 진성 비정질 실리콘막을 형성하는 제3단계; 절연막을 형성하는 제4단계; 절연막과 진성 결정성 실리콘막을 에칭하여 소오스/드레인 영역에 콘택트 홀을 형성하는 제5단계; 비정질 실리콘의 결정화를 가속하는 촉매원소를 함유한 층을 기판상에 형성하는 제6단계; 열어닐링을 통해 진성 비정질 실리콘막을 결정화시킴으로써 실제 진성인 결정성 실리콘막을 형성하는 제7단계; 및 게이트 전극 및 소오스/드레인 전극을 형성하는 제8단계를 포함하는 반도체 장치의 제조방법.Forming a N-type or P-type amorphous silicon film; Etching a N-type or P-type amorphous silicon film to form a pair of semiconductor regions providing source / drain regions; A third step of forming an intrinsic amorphous silicon film; A fourth step of forming an insulating film; Etching the insulating film and the intrinsic crystalline silicon film to form contact holes in the source / drain regions; A sixth step of forming on the substrate a layer containing a catalytic element for accelerating crystallization of amorphous silicon; A seventh step of forming an intrinsic crystalline silicon film by crystallizing the intrinsic amorphous silicon film through open annealing; And an eighth step of forming a gate electrode and a source / drain electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
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