KR950034611A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR950034611A
KR950034611A KR1019950011654A KR19950011654A KR950034611A KR 950034611 A KR950034611 A KR 950034611A KR 1019950011654 A KR1019950011654 A KR 1019950011654A KR 19950011654 A KR19950011654 A KR 19950011654A KR 950034611 A KR950034611 A KR 950034611A
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semiconductor device
insulating film
wiring layer
metal wiring
metal
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KR0161774B1 (en
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이사오 무라카미
아츠히로 카지야
노부유키 타케나카
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스기야마 카즈히코
마츠시다덴시고교 가부시기가이샤
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 분리영역(52)의 실리콘기판(55)보다 상층에 층간절연막을 존재시키는 동시에, 경계영역(63)에 실리콘기판(55)과 도통하는 적어도 1열의 금속콘택트부(53), (53´)를 구비하고, 이 금속콘택트부는 메탈배선층(60)과 도통하고, 전기절연피막(57)으로 덮음으로써, 치핑이 없는 스크라이브를 할 수 있고, 실리콘기판의 손상이 없고, 기판의 전위고정이 용이하고 고신뢰성의 반도체장치를 제공하는 것을 목적으로 하며, 그 구성에 있어서, 반도체장치본체(62)와 분리영역(52)과의 경계영역(63)에 텅스텐을 매립한 폭 0.01∼1㎛의 콘택트(53), (53´)를 반도체장치본체(62)의 외주를 포위해서 형성하고, 실리콘기판(55)의 전위를 고정하기 위한 제1메탈배선층(60)과 제2메탈배선층(61)을 그위에 형성한다. 또 스크라이브레인영역(52)에는 산화실리콘막(58´)과 층간절연막(51)을 형성하는 것을 특징으로 하는 것이다.According to the present invention, an interlayer insulating film is formed above the silicon substrate 55 of the isolation region 52 and at least one metal contact portion 53, 53 connected to the silicon substrate 55 in the boundary region 63. ”), And the metal contact portion is electrically conductive with the metal wiring layer 60 and covered with the electrical insulating film 57, so that a chipping can be performed without chipping, and there is no damage to the silicon substrate, and the potential fixation of the substrate is improved. An object of the present invention is to provide an easy and highly reliable semiconductor device, and in its configuration, a width of 0.01 to 1 탆 in which tungsten is embedded in a boundary region 63 between the semiconductor device body 62 and the separation region 52. The first metal wiring layer 60 and the second metal wiring layer 61 for forming the contacts 53 and 53 'surrounding the outer circumference of the semiconductor device body 62 to fix the potential of the silicon substrate 55. Form on it. The silicon oxide film 58 'and the interlayer insulating film 51 are formed in the scribe-lane area 52.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 실시예 1의 반도체장치를 표시한 단면도, 제2도는 본 발명의 실시예 1의 반도체장치를 표시한 단면도.1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

Claims (20)

실리콘기판상의 반도체장치본체영역과 분리영역(스크라이브레인영역)과 상기 2영역의 사이의 경계영역을 포함한 반도체장치에 있어서, 상기 분리영역의 상기 실리콘기판보다 상층에 층간절연막을 존재시키는 동시에 상기 경계영역에 상기 실리콘기판과 도통하는 적어도 1일의 금속콘택트부를 구비하고, 상기 금속콘택트부는 메탈배선층과 도통하고 있고, 또한 상기 메탈배선층은 전기절연피막으로 덮어 있는 것을 특징으로 하는 반도체장치.A semiconductor device including a semiconductor device body region and a separation region (scribe lane region) and a boundary region between the two regions on a silicon substrate, wherein an interlayer insulating film is formed above the silicon substrate of the separation region and at the same time. And at least one metal contact portion in electrical contact with the silicon substrate, wherein the metal contact portion is in electrical contact with the metal wiring layer, and the metal wiring layer is covered with an electrical insulating film. 제1항에 있어서, 금속콘택트부가 텅스텐 및 텅스텐을 함유한 합금으로부터의 선택되는 적어도 1개의 금속으로 형성되어 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the metal contact portion is formed of at least one metal selected from tungsten and an alloy containing tungsten. 제1항에 있어서, 금속콘택트부가 상기 반도체장치본체의 외주를 포위하는 위치에 존재하는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein a metal contact portion is present at a position surrounding the outer circumference of the semiconductor device body. 제1항에 있어서, 금속콘택트부의 폭이 0.01㎛이상 1㎛이하의 범위인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein a width of the metal contact portion is in a range of 0.01 µm or more and 1 µm or less. 제3항에 있어서, 반도체장치본체의 외주를 포위하는 금속콘택트부가 1열 또는 2열인 것을 특징으로 하는 반도체장치.4. The semiconductor device according to claim 3, wherein the metal contact portions surrounding the outer circumference of the semiconductor device body are one or two rows. 제1항에 있어서, 메탈배선층이, 제1메탈배선층 및 그 표면의 제2메탈배선층으로 이루어지고, 또한 상기 제1메탈배선층과 제2메탈배선층은 도통하고 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the metal wiring layer is composed of a first metal wiring layer and a second metal wiring layer on the surface thereof, and the first metal wiring layer and the second metal wiring layer are conductive. 제1항에 있어서, 실리콘기판과 층간절연막의 사이에 산화실리콘막을 존재시킨 것을 특징으로 하는 반도체장치.A semiconductor device according to claim 1, wherein a silicon oxide film is provided between the silicon substrate and the interlayer insulating film. 제1항에 있어서, 층간절연막이 산화실리콘을 주성분으로 하는 막인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the interlayer insulating film is a film mainly composed of silicon oxide. 제1항에 있어서, 층간절연막의 두께가 0.1㎛이상∼1.0㎛의 범위인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the thickness of the interlayer insulating film is in a range of 0.1 µm or more and 1.0 µm. 제1항에 있어서, 메탈배선층을 덮는 전기절연피막이 질화실리콘막인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein the electrical insulating film covering the metal wiring layer is a silicon nitride film. 실리콘기판상의 반도체장치본체영역과 분리영역(스크라이브레인영역)과 상기 2영역의 사이의 경계영역을 포함한 반도체장치의 제조방법에 있어서, A. 실리콘기판의 표면에 화학기상성장(이하)법에 의해 층간절연막을 형성하고, B. 에칭법에 의해 상기 층간절연막에 실리콘기판까지 도달하는 홈부를 형성하고, 상기 홈부부분에 금속을 대립해서 금속콘택트부를 형성하고, C. 상기 금속콘택트부의 표면에 에칭법을 사용해서 메탈배선층을 형성하고, D. 상기 메탈배선층의 표면을 전기절연피막으로 덮음으로써 분리영역을 형성하는 것을 특징으로 하는 반도체장치.A method of manufacturing a semiconductor device including a semiconductor device body region and a separation region (scribe lane region) and a boundary region between the two regions on a silicon substrate, comprising the steps of: A. Chemical vapor deposition (hereinafter referred to) on the surface of a silicon substrate; An interlayer insulating film is formed, and B. a groove portion reaching the silicon substrate is formed in the interlayer insulating film by an etching method, a metal contact portion is formed by opposing a metal in the groove portion, and C. an etching method on the surface of the metal contact portion. And forming a metal wiring layer, and D. forming a separation region by covering the surface of the metal wiring layer with an electrical insulating film. 제11항에 있어서, 금속콘택트부를 텅스텐 및 텅스텐을 함유한 합금으로부터의 선택되는 적어도 1개의 금속으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.12. The method of manufacturing a semiconductor device according to claim 11, wherein the metal contact portion is formed of at least one metal selected from tungsten and an alloy containing tungsten. 제11항에 있어서, 금속콘택트부가 상기 반도체장치본체의 외주를 포위하는 위치에 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 11, wherein a metal contact portion is formed at a position surrounding the outer circumference of the semiconductor device body. 제11항에 있어서, 금속콘택트부의 폭을 0.01㎛이상 1㎛이하의 범위로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 11, wherein the width of the metal contact portion is formed in a range of 0.01 µm or more and 1 µm or less. 제13항에 있어서, 반도체장치본체의 외주를 포위하는 금속콘택트부를 1열 또는 2열로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 13, wherein the metal contact portions surrounding the outer circumference of the semiconductor device body are formed in one or two rows. 제11항에 있어서, 전기절연피막에 에칭법을 사용해서 메탈배선층까지 도달하는 홈부를 형성하고 상기 홈부부분에 제2메탈배선층을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.12. The method of manufacturing a semiconductor device according to claim 11, wherein a groove portion reaching the metal wiring layer is formed in the electrically insulating film by an etching method, and a second metal wiring layer is formed in the groove portion. 제11항에 있어서, 실리콘기판과 층간절연막과의 사이의 반도체장치본체영역의 단부에, 가열산화법에 의해 산화실리콘으로 이루어진 필드산화막을 형성하는 것을 특징으로 하는 반도체장치의 제조방법.12. The method of manufacturing a semiconductor device according to claim 11, wherein a field oxide film made of silicon oxide is formed at the end of the semiconductor device body region between the silicon substrate and the interlayer insulating film by a heat oxidation method. 제11항에 있어서, 층간절연막을 산화실리콘을 주성분으로 하는 막으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.12. The method of manufacturing a semiconductor device according to claim 11, wherein the interlayer insulating film is formed of a film containing silicon oxide as a main component. 제11항에 있어서, 층간절연막의 두께를 0.1㎛이상∼1.0㎛의 범위로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 11, wherein the thickness of the interlayer insulating film is formed in a range of 0.1 µm or more to 1.0 µm. 제11항에 있어서, 메탈배선층을 덮는 전기절연피막을 질화실리콘막으로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.12. The method of manufacturing a semiconductor device according to claim 11, wherein an electrical insulating film covering the metal wiring layer is formed of a silicon nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950011654A 1994-05-16 1995-05-12 Semiconductor device and manufacture thereof KR0161774B1 (en)

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