KR950033811A

KR950033811A - Computing Devices on Galois Field

Info

Publication number: KR950033811A
Application number: KR1019940010093A
Authority: KR
Inventors: 주태식; 이석정; 변형남
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-05-09
Filing date: 1994-05-09
Publication date: 1995-12-26
Also published as: KR0147588B1

Abstract

본 발명은 갈로이스 필드상에서의 연산장치를 공개한다. 그 회로는 갈로이스 필드상의 (αⁱ)², (αⁱ)^1/2, (αⁱ)³,의 연산을 수행하기 위한 독특한 회로 구성을 가지도록 함으로써 회로를 간략하하고 연산 시간을 줄일 수 있다.The present invention discloses a computing device on a galloise field. The circuit simplifies the circuit and reduces computation time by allowing it to have a unique circuit configuration for performing operations on (Ga) fields of (α ⁱ ) ² , (α ⁱ ) ^1/2 , and (α ⁱ ) ³ . have.

Description

Computing Devices on Galois Field

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제13도는 본 발명의 계수를 연산회로를 이용한 연산회로의 블럭도이다.13 is a block diagram of a calculation circuit using the calculation circuit of the present invention.

Claims

A first buffer for buffering the second input signal and outputting a coefficient of α ⁷ ; A first XOR gate for inputting and ORing the fourth and sixth input signals; A second XOR gate for inputting the seventh input signal and the output signal of the first XOR gate and performing exclusive OR to output a coefficient of α ⁶ ; A second buffer for buffering the sixth input signal and outputting a coefficient of α ⁵ ; A third XOR gate for inputting and ORing the third input signal and the fifth input signal; A fourth XOR gate for exclusively ORing the sixth input signal and the output signal of the third XOR gate; A fifth XOR gate for outputting a coefficient of α ⁴ by exclusively ORing the fifth input signal and the output signal of the ^fourth XOR gate; A sixth XOR gate for inputting the fifth and seventh input signals to perform an exclusive OR to output a coefficient of α ³ ; A seventh XOR gate for inputting and ORing the second and fifth input signals; An eighth XOR gate for inputting and ORing the sixth input signal and the output signal of the seventh XOR gate; A ninth XOR gate for inputting the seventh input signal and the output signal of the eighth XOR gate and performing exclusive OR to output a coefficient of α ² ; A third buffer for inputting and buffering an eighth input signal and outputting a coefficient of α ¹ ; A tenth XOR gate for inputting and ORing the first and fifth input signals; An eleventh XOR gate for exclusively ORing the seventh input signal and the output signal of the tenth XOR gate; Section 8 of the input signal and the output signal exclusive OR gate 11XOR to claim 12XOR comprising the gate (α ¹⁾ of the ^second arithmetic circuit for outputting a coefficient α ⁰ a.

A first buffer for buffering the second input signal and outputting a coefficient of α ⁷ ; A second buffer for inputting and buffering an eighth input signal to output a coefficient of α ⁶ ; A third buffer for inputting and buffering a seventh input signal to output a coefficient of α ⁵ ; A first XOR gate for inputting the fourth and eighth input signals to perform an exclusive OR and output a coefficient of α ⁴ ; A second XOR gate for inputting and ORing the sixth and seventh input signals; A third XOR gate for outputting a coefficient of α ³ by exclusively ORing the eighth input signal and the output signal of the second XOR gate; A fourth XOR gate for inputting and ORing the second and fourth input signals; A fifth XOR gate for inputting and ORing the fifth input signal and the output signal of the fourth XOR gate; A sixth XOR gate for inputting and ORing the sixth input signal and the output signal of the fifth XOR gate; A seventh XOR gate for inputting an eighth input signal and an output signal of a sixth XOR gate and performing an exclusive AND to output a coefficient of α ² ; An eighth XOR gate for inputting and ORing the third and fourth input signals; A ninth XOR gate for inputting the sixth input signal and the output signal of the eighth XOR gate and performing exclusive OR to output a coefficient of α ¹ ; A tenth XOR gate for inputting and ORing the first and second input signals; The fourth input signal and the input to the output signal of the exclusive OR gate 10XOR and comprising the first 11XOR gate for outputting a coefficient α ⁰ (α ¹⁾ ^1/2 computation circuit.

A first XOR gate for input-exclusive ORing the second and third input signals; A second XOR gate for inputting and ORing the fourth and fifth input signals; A third XOR gate for inputting and ORing the third and fifth input signals; A fourth XOR gate for inputting and ORing the first and second input signals; A fifth XOR gate for inputting and ORing the first and third input signals; A sixth XOR gate for inputting and ORing the fourth input signal and the output signal of the fourth XOR gate; A seventh XOR gate for inputting and ORing the sixth input signal and the output signal of the fifth XOR gate; An eighth XOR gate for inputting and ORing the sixth input signal and the output signal of the sixth XOR gate; A ninth XOR gate for inputting and ORing the seventh input signal and the output signal of the seventh XOR gate; A first AND gate for inputting and ORing the fourth input signal and the output signal of the first XOR gate; A second AND gate for inputting and ORing the fifth input signal and the output signal of the second XOR gate; A third AND gate for inputting and ORing the sixth input signal and the output signal of the third XOR gate; A fourth AND gate for inputting and ORing the seventh input signal and the output signal of the eighth XOR gate; A fifth AND gate for inputting and ORing the eighth input signal and the output signal of the ninth XOR gate; An eleventh XOR gate for exclusively ORing the output signals of the first and second AND gates; A twelfth XOR gate for exclusively logic output signals of the tenth and eleventh XOR gates; An α ⁷ coefficient generator circuit having a 13XOR gate for exclusively ORing the output signals of the 12th XOR gate and the fifth AND gate; A fourteenth XOR gate for inputting and ORing the second and third input signals; A fifteenth XOR gate for inputting and ORing the first and second input signals; A sixteenth XOR gate for inputting and ORing the third and fourth input signals; A seventeenth XOR gate for inputting and ORing the sixth and seventh input signals; An eighteenth XOR gate for inputting and ORing the fifth input signal and the output signal of the fourteenth XOR gate; A nineteenth XOR gate for inputting and ORing the third input signal and the output signal of the fifteenth XOR gate; A 20th XOR gate for inputting and ORing the fifth input signal and the output signal of the 16th XOR gate; A twenty-first XOR gate for exclusively ORing the eighth input signal and the output signal of the seventeenth XOR gate; A twenty-second XOR gate for inputting and ORing the fourth input signal and the output signal of the nineteenth XOR gate; A twenty-third XOR gate for exclusively ORing the sixth input signal and an output signal of the twenty-XOR gate; A sixth AND gate for inputting and ANDing the first and fourth input signals; a seventh AND gate for inputting and ANDing the output signal of the fifth input signal and the eighteenth XOR gate; A ninth AND gate for inputting and ORing the sixth input signal and the output signal of the twenty-second XOR gate; A tenth AND gate for inputting and ORing the eighth input signal and the output signal of the twenty-first XOR gate; A twenty-fourth XOR gate for exclusively ANDing the third input signal and the output signal of the sixth AND gate; a twenty-five XOR gate for exclusively ORing the output signals of the seventh and eighth AND gates; A 26th XOR gate for exclusively ORing the output signals of the ninth and tenth AND gates; A 27th XOR gate for exclusively ORing the output signals of the 24th and 25th XOR gates; 25, the gate output signal 26XOR claim ⁶ 28XOR the α coefficient generation circuit having a gate for the exclusive OR to generate the coefficients α of the ^6; A 29XOR gate for inputting and ORing the second and fourth input signals; A thirty-XOR gate for inputting and ORing the second and third input signals; A 31XOR gate for inputting and ORing the second and third input signals; A 32XOR gate for inputting and ORing the third and fourth input signals; A thirty-third XOR gate for inputting and ORing the first and seventh input signals; A 34XOR gate for exclusively ORing the fourth input signal with the output signal of the 31XOR gate; A 36XOR gate for inputting and ORing the seventh input signal and the output signal of the 32nd XOR gate; A 37XOR gate for inputting and ORing the sixth input signal and the output signal of the 34XOR gate; An eleventh AND gate for inputting and ORing the second and third input signals; An eleventh AND gate for exclusively ANDing the fourth input signal with the output signal of the 29th XOR gate: a twelfth AND gate for inputting and ANDing the fourth input signal and the output signal of the 29th XOR gate; A thirteenth AND gate for inputting and ORing the fifth input signal and the output signal of the thirtieth XOR gate; A fourteenth AND gate for inputting and ORing the sixth input signal and the output signal of the 35 th XOR gate; A fifteenth AND gate for inputting and ORing the seventh input signal and the output signal of the thirty-fifth XOR gate; A sixteenth AND gate for inputting and ORing the eighth input signal and the output signal of the 36XOR gate; A 38XOR gate for exclusive ORing the output signals of the eleventh and twelfth AND gates; A 39th XOR gate for exclusively ORing the output signals of the 13th and 14th AND gates; A 40XOR gate for exclusively ORing the output signals of the 15th and 16th AND gates; A 41XOR gate for exclusively ORing the output signals of the 38th and 39XOR gates; 40, the gate 41XOR claim 42XOR gate 119, a coefficient generation circuit having an α ⁵ for the exclusive-OR output signal to generate a coefficient α of ^5; A 43XOR gate for inputting and ORing the first and second input signals; A 44XOR gate for inputting and ORing the third and fourth input signals; A 45th XOR gate for inputting and ORing the second and fourth input signals; A 46XOR gate for inputting and ORing the first and third input signals; A 48XOR gate for inputting and ORing the second and fifth input signals; A 49th XOR gate for inputting and ORing the fifth input signal and the output signal of the 46th XOR gate; A 50th XOR gate for inputting and ORing the fourth input signal and the output signal of the 47th XOR gate; A 51XOR gate for inputting and ORing the fourth input signal and the output signal of the 48XOR gate; A 52XOR gate for exclusively ORing the eighth input signal and the output signal of the 51XOR gate; A seventeenth AND gate for exclusively ANDing the third input signal with the output signal of the 43rd XOR gate: an eighteenth AND gate for inputting and ANDing the fourth input signal and the output signal of the 44th XOR gate; A 19th AND gate for inputting and ORing the fifth input signal and the output signal of the 45th XOR gate; A 20th AND gate for inputting and ORing the sixth input signal and the output signal of the 49th XOR gate; A twenty-first AND gate for inputting and ORing the sixth input signal and the output signal of the 49th XOR gate; A 22nd AND gate for inputting and ORing an eighth input signal and an output signal of the 526XOR gate; A 53XOR gate for exclusively ORing the output signals of the 17th and 18th AND gates; A 54XOR gate for exclusively ORing the output signals of the 19th and 20th AND gates; A 55th XOR gate for exclusively ORing the output signals of the twenty-first and twenty-second AND gates; A 56th XOR gate for exclusively ORing the output signals of the 53rd and 54th XOR gates; 55, the gate output signal 56XOR claim 57XOR the α4 coefficient generation circuit having a gate for the exclusive OR to generate the coefficients α of the ^4; A 58XOR gate for inputting and ORing the first and third input signals; A 59XOR gate for inputting and ORing the first and second input signals; A 60XOR gate for inputting and ORing the second and fourth input signals; A 61XOR gate for inputting and ORing the first and second input signals; A sixty-second XOR gate for inputting and ORing the second and fourth input signals; A 63rd XOR gate for inputting and ORing the fourth input signal and the output signal of the 58th XOR gate; A 64XOR gate for inputting and ORing the third input signal and the output signal of the 59th XOR gate; A 65th XOR gate for inputting and ORing the fourth input signal and the output signal of the 61st XOR gate; A 66XOR gate for inputting and ORing the fifth input signal and the output signal of the 62XOR gate; A 67th XOR gate for inputting and ORing the fourth input signal and the output signal of the 64th XOR gate; An 68th XOR gate for inputting and ORing the seventh input signal and the output signal of the 65th XOR gate; A 69th XOR gate for inputting and ORing the seventh input signal and the output signal of the 64th XOR gate; A seventy-XOR gate for inputting and ORing the fifth input signal and the output signal of the 67-th XOR gate; A 71XOR gate for exclusively ORing the seventh input signal and the output signal of the 68th XOR gate; A twenty-third AND gate for exclusively ANDing the fourth input signal with the output signal of the 63rd XOR gate: a twenty-fourth AND gate for inputting and ANDing the fifth input signal and the output signal of the seventieth XOR gate; A 25th AND gate for inputting and ORing the sixth input signal and the output signal of the 60th XOR gate; A 26th AND gate for inputting and ORing the sixth input signal and the output signal of the 71XOR gate; A 27th AND gate for inputting and ORing the eighth input signal and the output signal of the 69th XOR gate; A 72XOR gate for inputting and ORing the second input signal and the output signal of the 23rd AND gate; A 73 th XOR gate for exclusively ORing the output signals of the 24 th and 25 th AND gates; A 74XOR gate for exclusively ORing the output signals of the 26th and 27th AND gates; A 75 th XOR gate for inputting and ORing the output signals of the 72 th and 73 th XOR gates; An α ³ coefficient generation circuit having a 76XOR gate for inputting and exclusively ORing an output signal of a 74th, 75XOR gate; A 77XOR gate for inputting and ORing the first and fourth input signals; A 78XOR gate for exclusively ORing the first and third input signals; A 79XOR gate for exclusively ORing the first and third input signals; An 80XOR gate for inputting and ORing the second and third input signals; An 82XOR gate for inputting and ORing the fifth input signal and the output signal of the 77XOR gate; An 83rd XOR gate for inputting and ORing the fifth input signal and the output signal of the 79th XOR gate; A 65th XOR gate for inputting and ORing the fourth input signal and the output signal of the 80th XOR gate; An 84th XOR gate for inputting and ORing the fourth input signal and the output signal of the 80th XOR gate; An 85th OR gate for inputting and ORing the fifth input signal and the output signal of the 82XOR gate; An 86XOR gate for inputting and ORing the sixth input signal and the output signal of the 83rd XOR gate; An 87th XOR gate for inputting and ORing the seventh input signal and the output signal of the 84th XOR gate; A 88th XOR gate for exclusively ORing the sixth input signal and the output signal of the 85th XOR gate; An 89th XOR gate for exclusively ORing the seventh input signal with the output signal of the 86th XOR gate; A 90th XOR gate for exclusively ORing the eighth input signal and the output signal of the 87th XOR gate; A 28AND gate for ANDing the first and second input signals; A 29AND gate for ANDing the first and third input signals; A 30AND gate for ANDing the third and fourth input signals; A thirty-first AND gate for exclusively ANDing the fifth input signal with the output signal of the 81 th XOR gate: a thirty-second AND gate for inputting and ANDing the sixth input signal and the output signal of the 88 th XOR gate; A thirty-third AND gate for inputting and ORing the seventh input signal and the output signal of the 89th XOR gate; A 34th AND gate for inputting and ORing the eighth input signal and the output signal of the 90th XOR gate; A 91XOR gate for exclusively ORing the output signals of the 28th and 29th AND gates; A 92XOR gate for exclusively ORing the output signals of the 30th and 31st AND gates; A 93XOR gate for exclusively ORing the output signals of the 32nd and 33rd AND gates; A 94XOR gate for exclusively ORing the output signals of the 91st and 92nd AND gates; A 92XOR gate for exclusively ORing the output signals of the 93XOR gate and the 34AND AND gate; 94, the gate output signal α 95XOR ³ coefficient generation circuit having a first input to gate 96XOR for generating coefficient α ² to the exclusive OR of; A 97XOR gate for inputting and ORing the third and fourth input signals; A 98XOR gate for exclusively ORing the second and third input signals; A 99XOR gate for inputting and ORing the first and fourth input signals; A 100XOR gate for inputting and ORing the sixth input signal and the output signal of the 97th XOR gate; A 101XOR gate for inputting and ORing the fourth input signal and the output signal of the 98XOR gate; A 102XOR gate for inputting and ORing the sixth input signal and the output signal of the 99th XOR gate; A 103XOR gate for inputting and ORing the fifth input signal and the output signal of the 101XOR gate; A 104XOR gate for inputting and ORing the sixth input signal and the output signal of the 102XOR gate; A 105XOR gate for exclusively ORing the seventh input signal and the output signal of the 104XOR gate; A 35AND gate for ANDing the first and second input signals; A 36AND gate for ANDing the second and fifth input signals; A 37th AND gate for ANDing the sixth input signal and the output signal of the 101XOR gate: a 38th AND gate for ANDing the seventh input signal and the output signal of the 103XOR gate; A 39th AND gate for ANDing the eighth input signal and the output signal of the 105XOR gate; A 106XOR gate for exclusively ORing the fourth input signal with the output signal of the 35th AND gate; A 107XOR gate for exclusively ORing the output signals of the 36th and 37th AND gates; A 108XOR gate for exclusive ORing the output signals of the 38th and 39th AND gates; A 109XOR gate for exclusively ORing the output signals of the 102- and 103-AND gates; Article 108, a coefficient generation circuit of the ^first α having a first gate 109XOR claim 111XOR gate for generating an output signal coefficient α ² of the exclusive OR; A 111XOR gate for inputting and ORing the first and third input signals; A 112XOR gate for inputting and ORing the third and fourth input signals; A 113XOR gate for inputting and ORing the first and third input signals; A 114XOR gate for inputting and ORing the first and fourth input signals; A 115XOR gate for exclusively ORing the fifth input signal and the output signal of the 111XOR gate; A 116XOR gate for inputting and ORing the fourth input signal and the output signal of the 113XOR gate; A 117XOR gate for exclusively ORing the fifth input signal with the output signal of the 114XOR gate; A 118XOR gate for exclusively ORing the fifth input signal and the output signal of the 116XOR gate; A 119XOR gate for exclusively ORing the eighth input signal and the output signal of the 117XOR gate; A 120XOR gate for exclusively ORing the seventh input signal and the output signal of the 118XOR gate; A 40th AND gate for ANDing the third and fourth input signals; A 41th AND gate for ANDing the fifth input signal and the output signal of the 115XOR gate: a 42nd AND gate for ANDing the sixth input signal and the output signal of the 112XOR gate; A 43th AND gate for ANDing the seventh input signal and the output signal of the 120XOR gate; A 44th AND gate for ANDing the eighth input signal and the output signal of the 119XOR gate; A 121XOR gate for exclusively ORing the first input signal and the output signal of the 40th AND gate; A 122XOR gate for exclusively ORing the output signals of the forty-first and forty-second AND gates; A 123XOR gate for exclusively ORing the output signals of the 43rd and 44th AND gates; A 124XOR gate for exclusively ORing the output signals of the 121nd and 122nd AND gates; (Α ¹ ) ³ arithmetic circuit comprising an α ⁰ coefficient generating circuit having a 125 XOR gate for generating an α ⁰ coefficient by exclusively ORing the output signals of the 123th and 124XOR gates.

A first XOR gate for input-exclusive ORing the first and second input signals; A second XOR gate for inputting and ORing the first and third input signals; A third XOR gate for inputting and ORing the first and fourth input signals; A fourth XOR gate for inputting and ORing the second and third input signals; A fifth XOR gate for inputting and ORing the second and fourth input signals; A sixth XOR gate for inputting and ORing the second and fifth input signals; A seventh XOR gate for inputting and ORing the second and fourth input signals; An eighth XOR gate for inputting and ORing the third and fifth input signals; A ninth XOR gate for inputting and ORing the third and seventh input signals; A tenth XOR gate for inputting and ORing the fourth and fifth input signals; An eleventh XOR gate for inputting and ORing the sixth and seventh input signals; A twelfth XOR gate for inputting and ORing the output signal of the first XOR gate and the third input signal; A thirteenth XOR gate for inputting and ORing the output signal of the first XOR gate and the fourth input signal; A fourteenth XOR gate for inputting and ORing the output signal of the second XOR gate and the fourth input signal; A fifteenth XOR gate for inputting and ORing the output signal of the second XOR gate and the fifth input signal; A sixteenth XOR gate for inputting and ORing the output signal of the second XOR gate and the sixth input signal; A seventeenth XOR gate for inputting and ORing the output signal of the third XOR gate and the fifth input signal; An eighteenth XOR gate for inputting and ORing the output signal of the fourth XOR gate and the fourth input signal; A nineteenth XOR gate for inputting and ORing the output signal of the fourth XOR gate and the fifth input signal; A 20th XOR gate for inputting and ORing the output signal of the fifth XOR gate and the fifth input signal; A twenty-first XOR gate for inputting and ORing the output signal of the sixth XOR gate and the sixth input signal; A twenty-second XOR gate for inputting and ORing the output signal of the seventh XOR gate and the fifth input signal; A twenty-third XOR gate for inputting and ORing the output signal of the seventh XOR gate and the sixth input signal; A twenty-fourth XOR gate for inputting and ORing the output signal of the seventh XOR gate and the seventh input signal; A 25th XOR gate for inputting and ORing the output signal of the 7th XOR gate and the 7th input signal; A twenty-sixth XOR gate for inputting and ORing the output signal of the eleventh XOR gate and the eighth input signal; A 27th XOR gate for inputting and ORing the output signal of the 12th XOR gate and the fourth input signal; A twenty eighth XOR gate for inputting and ORing the output signal of the thirteenth XOR gate and the fifth input signal; A twenty-ninth XOR gate for inputting and ORing the output signal of the thirteenth XOR gate and the sixth input signal; A thirtieth XOR gate for inputting and ORing the output signal of the thirteenth XOR gate and the eighth input signal; A thirty-first XOR gate for inputting and ORing the output signal of the fourteenth XOR gate and the fifth input signal; A thirty-second XOR gate for inputting and ORing the output signal of the fifteenth XOR gate and the sixth input signal; A thirty-third XOR gate for inputting and ORing the output signal of the sixteenth XOR gate and the seventh input signal; A thirty-fourth XOR gate for inputting and ORing the output signal of the seventeenth XOR gate and the sixth input signal; A 35th XOR gate for inputting and ORing the output signal of the 17th XOR gate and the 7th input signal; A 36XOR gate for exclusively ORing the output signal of the 18th XOR gate and the fifth input signal; A 37XOR gate for inputting and ORing the output signal of the 18th XOR gate and the sixth input signal; A 38XOR gate for inputting and ORing the output signal of the 18th XOR gate and the seventh input signal; A 39th XOR gate for inputting and ORing the output signal of the 20th XOR gate and the seventh input signal; A 40XOR gate for inputting and ORing the output signal of the 22nd XOR gate and the 6th input signal; A 41st XOR gate for inputting and ORing the output signal of the 27th XOR gate and the fifth input signal; A 42XOR gate for inputting and ORing the output signal of the 28th XOR gate and the 7th input signal; A 43rd XOR gate for inputting and ORing the output signal of the 31st XOR gate and the 6th input signal; A 44th XOR gate for inputting and ORing the output signal of the 31st XOR gate and the 7th input signal; A 45th XOR gate for exclusively ORing the output signal of the 32nd XOR gate and the 7th input signal; A 46th XOR gate for exclusively ORing the output signal of the 34th XOR gate and the 7th input signal; A 47XOR gate for exclusively ORing an output signal of the 38XOR gate and an eighth input signal; A first AND gate for ANDing the eighth input signal and the output signal of the thirty-third XOR gate; A second AND gate for performing an AND operation on the seventh input signal and the output signal of the 29th XOR gate; A third AND gate for ANDing the sixth input signal and the output signal of the eighth XOR gate; A fourth AND gate for performing an AND operation on the fifth input signal and the output signal of the tenth XOR gate; A fifth AND gate for performing an AND operation on the fourth input signal and the output signal of the fourth XOR gate; A sixth AND gate for ANDing the eighth input signal and the output signal of the 26th XOR gate; A seventh AND gate for performing an AND operation on the seventh input signal and the output signal of the 40th XOR gate; An eighth AND gate for ANDing the sixth input signal and the output signal of the 27th XOR gate; A ninth AND gate for ANDing the fifth input signal with the output signal of the nineteenth XOR gate; A tenth AND gate for performing an AND operation on the fourth input signal and the first input signal; An eleventh AND gate for performing an AND operation on the eighth input signal and the output signal of the 28th XOR gate; A twelfth AND gate for ANDing the seventh input signal and the output signal of the twenty-fourth XOR gate; A thirteenth AND gate for ANDing the sixth input signal and the output signal of the 37XOR gate; A fourteenth AND gate for ANDing the fifth input signal and the output signal of the fourth XOR gate; A fifteenth AND gate for ANDing the fourth input signal with the output signal of the fifth XOR gate; A sixteenth AND gate for ANDing the third input signal and the second input signal; A seventeenth AND gate for ANDing the eighth input signal and the output signal of the thirtieth XOR gate; An eighteenth AND gate for ANDing the seventh input signal and the output signal of the twenty-first XOR gate; A nineteenth AND gate for ANDing the sixth input signal and the output signal of the fifteenth XOR gate; A 20th AND gate for ANDing the fifth input signal and the output signal of the fifth XOR gate; A twenty-first AND gate for performing an AND operation on the fourth input signal and the output signal of the seventh XOR gate; A twenty-second AND gate for performing an AND operation on the third input signal and the output signal of the first XOR gate; A twenty-third AND gate for ANDing the eighth input signal and the output signal of the 39th XOR gate; A twenty-fourth AND gate for ANDing the seventh input signal with the output signal of the 42nd XOR gate; A twenty-fifth AND gate for performing an AND operation on the sixth input signal and the output signal of the fifth XOR gate; A 26th AND gate for ANDing the fifth input signal with the output signal of the 41XOR gate; A 27th AND gate for ANDing the fourth input signal with the output signal of the 14th XOR gate; A 28th AND gate for ANDing the eighth input signal and the output signal of the 47th XOR gate; A twenty-ninth AND gate for ANDing the seventh input signal with the output signal of the 45th XOR gate; A thirtieth AND gate for ANDing the sixth input signal and the output signal of the 43rd XOR gate; A thirty-first AND gate for ANDing the fifth input signal with the output signal of the seventeenth XOR gate; A thirty-second AND gate for ANDing the fourth input signal and the third input signal; A thirty-third AND gate for performing an AND operation on the third input signal and the first input signal; A 34th AND gate for ANDing the second input signal with the first input signal; A thirty-third AND gate for ANDing the eighth input signal and the output signal of the 46th XOR gate; A 36th AND gate for ANDing the seventh input signal and the output signal of the 36XOR gate; A 37th AND gate for ANDing the sixth input signal and the output signal of the 24th XOR gate; A 38AND gate for ANDing the fifth input signal with the second input signal; A 39th AND gate for ANDing the first input signal and the second input signal; A 40th AND gate for ANDing the eighth input signal and the output signal of the 35th XOR gate; A 41st AND gate for ANDing the seventh input signal and the output signal of the 44th XOR gate; A 42nd AND gate for ANDing the sixth input signal and the output signal of the seventh XOR gate; A 43th AND gate for ANDing the fifth input signal and the output signal of the 15th XOR gate; A 44th AND gate for ANDing the third input signal and the fourth input signal; A 48XOR gate for exclusively ORing the output signals of the first and second AND gates; A 49th XOR gate for exclusively ORing the output signals of the sixth and seventh AND gates; A fifty-XOR gate for exclusively ORing the output signals of the eleventh and twelfth AND gates; A 51XOR gate for exclusively ORing the output signals of the 17th and 18th AND gates; A 52XOR gate for exclusively ORing the output signals of the 23rd and 24th AND gates; A 53rd XOR gate for exclusively ORing the output signals of the 28th and 29th AND gates; A 54th XOR gate for exclusively ORing the output signals of the 35th and 36th AND gates; A 55th XOR gate for exclusively ORing the output signals of the 40th and 41st AND gates; A 56 th XOR gate for exclusively ORing the output signals of the second AND gate and the 48 th XOR gate; A 57th XOR gate for exclusively ORing the output signals of the eighth AND gate and the 49th XOR gate; A 58th XOR gate for exclusively ORing the output signals of the 13th AND gate and the 50th XOR gate; A 59th XOR gate for exclusively ORing the output signals of the 19th AND gate and the 51XOR gate; A 60th XOR gate for exclusively ORing the output signals of the 25th AND gate and the 52nd XOR gate; A 61xXOR gate for exclusively ORing the output signals of the 30th AND gate and the 53XX gate; A sixty-second XOR gate for exclusively ORing the output signals of the 37th AND gate and the 54th XOR gate; A 63rd XOR gate for exclusively ORing the output signals of the 42nd AND gate and the 55th XOR gate; A 64 th XOR gate for exclusively ORing the output signals of the third AND gate and the 56 th XOR gate; A 65th XOR gate for exclusively ORing the output signals of the ninth AND gate and the 57th XOR gate; A 66th XOR gate for exclusively ORing the output signals of the 14th AND gate and the 58th XOR gate; A 67th XOR gate for exclusively ORing the output signals of the 20th AND gate and the 59th XOR gate; An 68th XOR gate for exclusively ORing the output signals of the 26th AND gate and the 60th XOR gate; A 69th XOR gate for exclusively ORing the output signals of the 31st AND gate and the 61st XOR gate; A seventy-XOR gate for exclusively ORing the output signals of the thirty-eight AND gate and the sixty-second XOR gate; A 71XOR gate for exclusively ORing the output signals of the 43th AND gate and the 63XX gate; A 72XOR gate for generating α ⁷ coefficients by exclusively ORing the output signals of the fifth AND gate and the 64XOR gate; A 73XOR gate for exclusively ORing the output signals of the 10th AND gate and the 65XOR gate; A 74th XOR gate for exclusively ORing the output signals of the 15th AND gate and the 66th XOR gate; A 75th XOR gate for exclusively ORing the output signals of the 21st AND gate and the 67th XOR gate; A 76XOR gate for exclusively ORing the output signals of the 27th AND gate and the 68XOR gate; A 77th XOR gate for exclusively ORing the output signals of the 32nd AND gate and the 69th XOR gate; A 78XOR gate for exclusively ORing the fourth input signal and the output signal of the 70XOR gate; A 79XOR gate for exclusively ORing the output signals of the 44th AND gate and the 71XOR gate; An 80XOR gate for generating α ⁶ coefficients by exclusive OR of the third input signal and the output signal of the 73XX gate; The 16AND to exclusive-OR the output signal of the AND gate and the second gate 74XOR 81XOR gate for generating a coefficient α ^5; An 82XOR gate for generating an α ⁴ coefficient by exclusively ORing the output signals of the 21st AND gate and the 75XOR gate; The second input signal to the exclusive-OR the output signal of the gate 76XOR claim 83XOR gate for generating a coefficient α ^3; An 84th XOR gate for exclusively ORing the output signals of the 33rd AND gate and the 77th XOR gate; An 85th XOR gate for generating an α ¹ coefficient by exclusively ORing the output signals of the 39th AND gate and the 78XOR gate; An 86XOR gate for generating an α ⁰ coefficient by exclusively ORing the first input signal and the output signal of the 79XOR gate; And a 87th XOR gate for generating an alpha ² coefficient by exclusively ORing the output signals of the 34th AND gate and the 84th XOR gate.

A first register for transmitting the first data as it is in response to the first control signal; Inversion calculation means for inverting the second data in response to the second control signal to generate a coefficient; Multiplication means for inputting and multiplying an output signal of said first register or said inversion calculation means by a second data; Adding means for inputting and adding an output signal of the multiplication means and third data; (Α ¹ ) ² arithmetic means for inputting an output signal of the addition means in response to a third control signal to perform a square operation to generate a coefficient; 4 in response to the control signal the output signal of said adding means ^{^{(α 1) (α 1)}} 1/2 computing means for generating a coefficient to perform the operation ^one-half; A fifth control signal in response to the output signal of said adding means ^{^{(α 1) (α 1)}} 3 operation means for generating a coefficient by performing a ^third operation; A second register for transmitting the output signal of the addition means as it is in response to a sixth control signal C ₄ ; And a register 580 for storing and outputting the (α ¹ ) ² , (α ¹ ) ^1/2 , (α ¹ ) ³ calculation means, and an output signal of the second register. Computation circuit on the field.

※ Note: The disclosure is based on the initial application.