KR950030596A - High resolution TV clock recovery circuit - Google Patents

High resolution TV clock recovery circuit Download PDF

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Publication number
KR950030596A
KR950030596A KR1019940007528A KR19940007528A KR950030596A KR 950030596 A KR950030596 A KR 950030596A KR 1019940007528 A KR1019940007528 A KR 1019940007528A KR 19940007528 A KR19940007528 A KR 19940007528A KR 950030596 A KR950030596 A KR 950030596A
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South Korea
Prior art keywords
analog
clock
signal
slicing
marker information
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KR1019940007528A
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Korean (ko)
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KR100283889B1 (en
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이호웅
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이헌조
엘지전자 주식회사
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  • Television Systems (AREA)

Abstract

본 발명은 고화질티브이의 클럭 리커버리회로에 관한 것으로, 종래에는 송신측으로부터 입력된 아날로그신호를 디지탈신호로 변환하는데 고속의 아날로그/디지탈 변환기를 사용하기 때문에 필연적으로 양자화에러를 유발시키고, 그 고속의 아날로그/디지탈 변환기가 고가이기 때문에 전체적인 제조원가가 상승하며, 아울러 아날로그/디지탈 변환기가 고속으로 동작하는 특성상 전력소모가 크고, 다른 한편으로는 수직기준신호를 저장하기 위해서 롬과 같은 별도의 메모리를 필요로 하기 때문에 이 또한 제조원가의 상승요인으로 작용한다는 문제점이 있다. 지금까지 설명한 바와 같이, 본 발명은 별도의 아날로그/디지탈 변환기를 사용하는 대신에 슬라이서를 이용함으로써 종래의 아날로그/디지탈 변환기를 사용함으로써 발생하였던 양자화에러를 줄일 수 있음과 아울러 전력손실을 경감할 수 있고, 수직동기신호를 기준정보로 사용할 때 롬 등을 필요로 하지 않으므로 제조원가가 경감되며, 신호를 아날로그화함으로써 많은 부분에서 공유가 가능하며 궁극적으로 브이엘에스아이(VLSI)의 구현이 간단해져 칩사이드가 줄어듦과 아울러 전력소비를 개선할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition clock recovery circuit. In the related art, a high-speed analog / digital converter is used to convert an analog signal input from a transmitting side into a digital signal, which inevitably causes a quantization error. Due to the high cost of digital converters, the overall manufacturing cost rises, and the analog / digital converters operate at high speed, resulting in high power consumption. On the other hand, a separate memory such as ROM is required to store vertical reference signals. Because of this, there is also a problem that acts as a rising factor of manufacturing costs. As described so far, the present invention can reduce power loss and reduce quantization error caused by using a conventional analog / digital converter by using a slicer instead of using a separate analog / digital converter. When using the vertical synchronous signal as reference information, no ROM is required, which reduces manufacturing costs, and by analogizing the signal, it can be shared in many parts, and ultimately, the implementation of VLSI is simplified, which reduces chip side. In addition, power consumption can be improved.

Description

고화질티브이의 클럭 리커버리회로High resolution TV clock recovery circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 고화질티브이이 클럭 리커버리회로의 블럭도, 제4도는 제3도 슬라이서의 동작 설명도.3 is a block diagram of the present invention high-definition clock recovery circuit, and FIG. 4 is a diagram illustrating the operation of the slicer of FIG.

Claims (2)

클럭신호에 따라 압축된 비디오신호원의 비디오정보를 프리코더를 통해 입력받아 마커정보와 함께 변조하여 수신측으로 송신하는 변조수단과, 상기 변조수단이 송신한 비디오정보와 마커정보가 튜닝되어 입력되어 오면 이를 소정의 이득에 따라 증폭하는 증폭/자동이득제어수단과 상기 증폭/자동이득제어수단이 증폭출력한 아날로그 데이타 및 마커정보를 슬라이싱하는 슬라이싱수단과, 상기 슬라이싱수단이 슬라이싱하여 출력하는 마커정보로부터 수평/수직동기신호 및 클럭신호를 만들어 내는 동기신호검출/클럭발생수단과, 상기 동기신호검출/클럭발생수단이 만들어 낸 수평/수직동기신호 및 클럭신호를 피엘엘부와 증폭기를 통해 입력받아 디바이딩하여 클럭정보를 발생하는 디바이딩수단을 구비한 것을 특징으로 하는 고화질티브이 클럭 리커버리회로.Modulation means for receiving video information of a video signal source compressed according to a clock signal through a precoder and modulating it together with marker information, and transmitting it to a receiving side; and when the video information and marker information transmitted by the modulation means are tuned and inputted, Amplification / auto gain control means for amplifying this according to a predetermined gain, slicing means for slicing analog data and marker information amplified by the amplification / auto gain control means, and horizontally from marker information slicing and outputting by the slicing means. The synchronous signal detection / clock generation means for generating the vertical synchronous signal and the clock signal, and the horizontal / vertical synchronous signal and the clock signal generated by the synchronous signal detection / clock generation means are received and divided through the PEL unit and the amplifier. High-definition clock reclocking, characterized in that it comprises a dividing means for generating clock information. Discard circuit. 제1항에 있어서, 슬라이싱수단은 증폭/자동이득제어수단의 아날로그 데이타를 +2.5〔V〕에서 슬라이싱하고, 마커정보를 -2.5〔V〕에서 슬라이싱하는 것을 특징으로 하는 고화질티브이의 클럭 리커버리회로.2. The high-definition clock recovery circuit according to claim 1, wherein the slicing means slices analog data of the amplification / auto gain control means at +2.5 [V] and slices marker information at -2.5 [V]. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is to be disclosed based on the initial application.
KR1019940007528A 1994-04-11 1994-04-11 High resolution TV clock recovery circuit Expired - Fee Related KR100283889B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940007528A KR100283889B1 (en) 1994-04-11 1994-04-11 High resolution TV clock recovery circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940007528A KR100283889B1 (en) 1994-04-11 1994-04-11 High resolution TV clock recovery circuit

Publications (2)

Publication Number Publication Date
KR950030596A true KR950030596A (en) 1995-11-24
KR100283889B1 KR100283889B1 (en) 2001-03-02

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