KR950030596A

KR950030596A - High resolution TV clock recovery circuit

Info

Publication number: KR950030596A
Application number: KR1019940007528A
Authority: KR
Inventors: 이호웅
Original assignee: 이헌조; 엘지전자 주식회사
Priority date: 1994-04-11
Filing date: 1994-04-11
Publication date: 1995-11-24
Also published as: KR100283889B1

Abstract

본 발명은 고화질티브이의 클럭 리커버리회로에 관한 것으로, 종래에는 송신측으로부터 입력된 아날로그신호를 디지탈신호로 변환하는데 고속의 아날로그/디지탈 변환기를 사용하기 때문에 필연적으로 양자화에러를 유발시키고, 그 고속의 아날로그/디지탈 변환기가 고가이기 때문에 전체적인 제조원가가 상승하며, 아울러 아날로그/디지탈 변환기가 고속으로 동작하는 특성상 전력소모가 크고, 다른 한편으로는 수직기준신호를 저장하기 위해서 롬과 같은 별도의 메모리를 필요로 하기 때문에 이 또한 제조원가의 상승요인으로 작용한다는 문제점이 있다. 지금까지 설명한 바와 같이, 본 발명은 별도의 아날로그/디지탈 변환기를 사용하는 대신에 슬라이서를 이용함으로써 종래의 아날로그/디지탈 변환기를 사용함으로써 발생하였던 양자화에러를 줄일 수 있음과 아울러 전력손실을 경감할 수 있고, 수직동기신호를 기준정보로 사용할 때 롬 등을 필요로 하지 않으므로 제조원가가 경감되며, 신호를 아날로그화함으로써 많은 부분에서 공유가 가능하며 궁극적으로 브이엘에스아이(VLSI)의 구현이 간단해져 칩사이드가 줄어듦과 아울러 전력소비를 개선할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-definition clock recovery circuit. In the related art, a high-speed analog / digital converter is used to convert an analog signal input from a transmitting side into a digital signal, which inevitably causes a quantization error. Due to the high cost of digital converters, the overall manufacturing cost rises, and the analog / digital converters operate at high speed, resulting in high power consumption. On the other hand, a separate memory such as ROM is required to store vertical reference signals. Because of this, there is also a problem that acts as a rising factor of manufacturing costs. As described so far, the present invention can reduce power loss and reduce quantization error caused by using a conventional analog / digital converter by using a slicer instead of using a separate analog / digital converter. When using the vertical synchronous signal as reference information, no ROM is required, which reduces manufacturing costs, and by analogizing the signal, it can be shared in many parts, and ultimately, the implementation of VLSI is simplified, which reduces chip side. In addition, power consumption can be improved.

Description

High resolution TV clock recovery circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 고화질티브이이 클럭 리커버리회로의 블럭도, 제4도는 제3도 슬라이서의 동작 설명도.3 is a block diagram of the present invention high-definition clock recovery circuit, and FIG. 4 is a diagram illustrating the operation of the slicer of FIG.

Claims

Modulation means for receiving video information of a video signal source compressed according to a clock signal through a precoder and modulating it together with marker information, and transmitting it to a receiving side; and when the video information and marker information transmitted by the modulation means are tuned and inputted, Amplification / auto gain control means for amplifying this according to a predetermined gain, slicing means for slicing analog data and marker information amplified by the amplification / auto gain control means, and horizontally from marker information slicing and outputting by the slicing means. The synchronous signal detection / clock generation means for generating the vertical synchronous signal and the clock signal, and the horizontal / vertical synchronous signal and the clock signal generated by the synchronous signal detection / clock generation means are received and divided through the PEL unit and the amplifier. High-definition clock reclocking, characterized in that it comprises a dividing means for generating clock information. Discard circuit.

2. The high-definition clock recovery circuit according to claim 1, wherein the slicing means slices analog data of the amplification / auto gain control means at +2.5 [V] and slices marker information at -2.5 [V].

※ Note: It is to be disclosed based on the initial application.