KR950030264A - Method for forming metal wirings for semiconductor devices - Google Patents

Method for forming metal wirings for semiconductor devices Download PDF

Info

Publication number
KR950030264A
KR950030264A KR1019940007662A KR19940007662A KR950030264A KR 950030264 A KR950030264 A KR 950030264A KR 1019940007662 A KR1019940007662 A KR 1019940007662A KR 19940007662 A KR19940007662 A KR 19940007662A KR 950030264 A KR950030264 A KR 950030264A
Authority
KR
South Korea
Prior art keywords
tungsten nitride
film
nitride film
contact opening
deposition
Prior art date
Application number
KR1019940007662A
Other languages
Korean (ko)
Other versions
KR970005684B1 (en
Inventor
김영선
박병률
박영욱
김용태
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019940007662A priority Critical patent/KR970005684B1/en
Publication of KR950030264A publication Critical patent/KR950030264A/en
Application granted granted Critical
Publication of KR970005684B1 publication Critical patent/KR970005684B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole

Abstract

반도체소자의 금속배선 형성방법이 개시되어 있다. 실리콘 기판상의 콘택 개구부에 오믹 층인 티타늄막을 형성하고, 상기 티타늄막 위에서, NH3플라즈마 처리를 하고, 상기 NH3플라즈마 처리된 티타늄막상에 확산 방지막인 텅스텐 질화막을 플라즈마 화학증착법으로 형성한다.A method of forming metal wirings in a semiconductor device is disclosed. A titanium film, which is an ohmic layer, is formed in the contact opening on the silicon substrate, NH 3 plasma treatment is formed on the titanium film, and a tungsten nitride film, which is a diffusion barrier film, is formed on the NH 3 plasma treated titanium film by plasma chemical vapor deposition.

플라즈마 화학증착법으로 텅스텐 질화막을 형성함으로써 단차도포성이 향상되고, 티타늄막을 형성함으로써 기판과 오믹 특성을 갖게되며, NH3플라즈마 처리를 실시함으로써 TiF3의 생성이 억제되어 콘택 저항을 감소시킨다.By forming the tungsten nitride film by the plasma chemical vapor deposition method, the step coating property is improved, and the titanium film is formed to have the ohmic characteristics with the substrate, and the NH 3 plasma treatment suppresses the production of TiF 3 , thereby reducing the contact resistance.

Description

반도체소자 금속배선 형성방법Method for forming metal wirings for semiconductor devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도 내지 제3F는 본 발명에 의한 금속배선 형성방법의 일 예를 설명하기 위한 단면도들이고; 제4도는 본 발명에 따르는 티타늄막과 실리콘 기판과의 콘택 특성을 측정한 그래프이다.3A to 3F are cross-sectional views illustrating an example of a method for forming metal wirings according to the present invention; 4 is a graph measuring contact characteristics between a titanium film and a silicon substrate according to the present invention.

Claims (16)

실리콘 기판상의 콘택 개구부에 티타늄을 증착하여 티타늄막을 형성하는 단계; 상기 티타늄막 형성후 NH3플라즈마 처리를 실시하는 단계; 상기 NH3플라즈마 처리된 티타늄막 위에 질화 텅스텐을 화학기상 증착 방법으로 증착하여 텅스텐 질화막을 형성하는 단계;를 구비하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.Depositing titanium into a contact opening on the silicon substrate to form a titanium film; Performing NH 3 plasma treatment after forming the titanium film; And depositing tungsten nitride on the NH 3 plasma treated titanium film by a chemical vapor deposition method to form a tungsten nitride film. 제1항에 있어서, 상기 텅스텐 질화막 위에 금속을 증착하여 금속층을 형성하고 상기 금속층을 열처리하여 리플로우 시키는 단계를 더 구비하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, further comprising depositing a metal on the tungsten nitride layer to form a metal layer, and heat treating and reflowing the metal layer. 제2항에 있어서, 상기 금속은 알루미늄(Al), 알루미늄합금, 구리(Cu), 금(Au), 은(Ag), 몰리브덴(Mo), 코발트(Co) 및 텅스텐(W)으로 구성된 군에서 선택된 어느 하나인 것을 특징으로 하는 반도체소자 금속배선 형성방법.According to claim 2, wherein the metal is in the group consisting of aluminum (Al), aluminum alloy, copper (Cu), gold (Au), silver (Ag), molybdenum (Mo), cobalt (Co) and tungsten (W). The semiconductor device metal wiring forming method, characterized in that any one selected. 제3항에 있어서, 상기 알루미늄합금은 알루미늄-1%실리콘 또는 알루미늄-0.5% 구리-1%실리콘인 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 3, wherein the aluminum alloy is aluminum-1% silicon or aluminum-0.5% copper-1% silicon. 제1항에 있어서, 상기 화학기상증착방법은 플라즈마 화학기상증착방법인 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, wherein the chemical vapor deposition method is a plasma chemical vapor deposition method. 제1항에 있어서, 상기 NH3플라즈마 처리는 300∼400℃의 증착온도, 90∼110W의 RF power, 0.05∼0.15Torr의 증착압력하에서 실시하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, wherein the NH 3 plasma treatment is performed at a deposition temperature of 300 to 400 ° C., an RF power of 90 to 110 W, and a deposition pressure of 0.05 to 0.15 Torr. 제6항에 있어서, 상기 증착온도는 350℃이고, 상기 RF power는 100W이고, 상기 증착압력은 0.1 Torr인 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 6, wherein the deposition temperature is 350 ° C., the RF power is 100 W, and the deposition pressure is 0.1 Torr. 제1항에 있어서, 상기 텅스텐 질화막은 200∼450℃의 증착온도, 30∼400W의 RF power, 0.05∼0.3 Torr의 증착압력하에서 형성하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, wherein the tungsten nitride film is formed at a deposition temperature of 200 to 450 ° C., an RF power of 30 to 400 W, and a deposition pressure of 0.05 to 0.3 Torr. 제8항에 있어서, 상기 증착온도는 350℃이고, 상기 RF power는 100W이고, 상기 증착압력은 0.1 Torr인 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 8, wherein the deposition temperature is 350 ° C., the RF power is 100 W, and the deposition pressure is 0.1 Torr. 제1항에 있어서, 상기 콘택 개구부의 크기는 0.25㎛ 이상인 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, wherein the contact opening has a size of 0.25 μm or more. 제2항에 있어서, 상기 텅스텐질화막 형성시 상기 텅스텐 질화물로 상기 콘택 개구부를 매몰시키는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 2, wherein the contact opening is buried in the tungsten nitride when the tungsten nitride film is formed. 제11항에 있어서, 상기 콘택 개구부의 크기는 0.25㎛ 이하인 것을 특징으로 하는 반도체소자 금속배선 형성방법.12. The method of claim 11, wherein the contact opening has a size of 0.25 µm or less. 제2항에 있어서, 상기 티타늄막 형성시 상기 티타늄 막을 콘택 개구부의 바닥부분에만 형성하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 2, wherein the titanium film is formed only at a bottom portion of the contact opening when the titanium film is formed. 제13항에 있어서, 상기 텅스텐 질화막 증착 후 상기 텅스텐 질화막의 에치 백(etch back)을 실시하여 상기 텅스텐 질화막으로 콘택 개구부를 매몰하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.15. The method of claim 13, wherein after the tungsten nitride film is deposited, the tungsten nitride film is etched back to bury the contact openings in the tungsten nitride film. 제1항에 있어서, 상기 텅스텐질화물로 콘택 개구부를 매몰시키고 상기 텅스텐질화막을 배선층으로 사용하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, wherein the contact opening is buried in the tungsten nitride and the tungsten nitride film is used as a wiring layer. 제1항 또는 제2항에 있어서, 상기 텅스텐 질화막 증착후 400℃ 이상의 온도에서 열처리를 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체소자 금속배선 형성방법.The method of claim 1, further comprising performing heat treatment at a temperature of 400 ° C. or higher after depositing the tungsten nitride film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019940007662A 1994-04-12 1994-04-12 Wiring method in semiconductor manufacturing KR970005684B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940007662A KR970005684B1 (en) 1994-04-12 1994-04-12 Wiring method in semiconductor manufacturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940007662A KR970005684B1 (en) 1994-04-12 1994-04-12 Wiring method in semiconductor manufacturing

Publications (2)

Publication Number Publication Date
KR950030264A true KR950030264A (en) 1995-11-24
KR970005684B1 KR970005684B1 (en) 1997-04-18

Family

ID=19380901

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940007662A KR970005684B1 (en) 1994-04-12 1994-04-12 Wiring method in semiconductor manufacturing

Country Status (1)

Country Link
KR (1) KR970005684B1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100248804B1 (en) * 1996-12-30 2000-03-15 김영환 A method for forming metal wire in semiconductor device
KR100266871B1 (en) * 1996-06-28 2000-10-02 김영환 Method of forming barrier in semiconductor device
KR100430682B1 (en) * 1996-12-31 2004-07-12 주식회사 하이닉스반도체 Method of forming metal line of semiconductor device for restraining reaction between metal lines
KR100510465B1 (en) * 1998-05-12 2005-10-24 삼성전자주식회사 Method for forming barrier metal layer in semiconductor device
KR100525903B1 (en) * 1998-06-05 2006-01-12 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100266871B1 (en) * 1996-06-28 2000-10-02 김영환 Method of forming barrier in semiconductor device
KR100248804B1 (en) * 1996-12-30 2000-03-15 김영환 A method for forming metal wire in semiconductor device
KR100430682B1 (en) * 1996-12-31 2004-07-12 주식회사 하이닉스반도체 Method of forming metal line of semiconductor device for restraining reaction between metal lines
KR100510465B1 (en) * 1998-05-12 2005-10-24 삼성전자주식회사 Method for forming barrier metal layer in semiconductor device
KR100525903B1 (en) * 1998-06-05 2006-01-12 주식회사 하이닉스반도체 Metal wiring formation method of semiconductor device

Also Published As

Publication number Publication date
KR970005684B1 (en) 1997-04-18

Similar Documents

Publication Publication Date Title
US5310602A (en) Self-aligned process for capping copper lines
KR0179822B1 (en) Interconnections structure of semiconductor device and method for manufacturing thereof
US4910169A (en) Method of producing semiconductor device
KR0147682B1 (en) Method for manufacturing metal wiring of semiconductor device
KR960015742A (en) Semiconductor device and manufacturing method thereof
KR970052931A (en) Tungsten nitride thin film formation method and metal wiring formation method using the same
KR100459332B1 (en) Metal wiring formation method of semiconductor device
KR950030264A (en) Method for forming metal wirings for semiconductor devices
KR930003256A (en) How to Form a Metallized Wiring Layer in a Semiconductor Integrated Circuit
US5528081A (en) High temperature refractory metal contact in silicon integrated circuits
US6646353B1 (en) Semiconductor device having reduced electromigration in copper lines with calcium-doped copper surfaces formed by using a chemical solution
US6623654B2 (en) Thin interface layer to improve copper etch stop
US8587128B2 (en) Damascene structure
KR100710201B1 (en) Method for forming metal line of semiconductor device
KR100560289B1 (en) Metal wiring formation method of semiconductor device
KR930001311A (en) Metal wiring layer formation method of a semiconductor device
KR19990015715A (en) Metal wiring layer formation method
US5350711A (en) Method of fabricating high temperature refractory metal nitride contact and interconnect structure
KR960030372A (en) Metal wiring formation method of semiconductor device
KR19990059074A (en) Metal wiring formation method of semiconductor device
KR100327092B1 (en) Formation Method of Copper Alloy Wiring of Semiconductor Device
KR19980075835A (en) Metal wiring formation method of semiconductor device
TW200411737A (en) Method of manufacturing an electronic device and electronic device
KR100399066B1 (en) Method for aluminium-alloy in semiconductor device
KR970063490A (en) METHOD FOR FORMING METAL WIRING IN SEMICONDUCTOR

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060728

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee