KR950027960A - How to Design a Butting Contact Mask - Google Patents

How to Design a Butting Contact Mask Download PDF

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Publication number
KR950027960A
KR950027960A KR1019940005777A KR19940005777A KR950027960A KR 950027960 A KR950027960 A KR 950027960A KR 1019940005777 A KR1019940005777 A KR 1019940005777A KR 19940005777 A KR19940005777 A KR 19940005777A KR 950027960 A KR950027960 A KR 950027960A
Authority
KR
South Korea
Prior art keywords
conductive layer
reflectance
size
contact mask
step height
Prior art date
Application number
KR1019940005777A
Other languages
Korean (ko)
Other versions
KR0126886B1 (en
Inventor
황준
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940005777A priority Critical patent/KR0126886B1/en
Publication of KR950027960A publication Critical patent/KR950027960A/en
Application granted granted Critical
Publication of KR0126886B1 publication Critical patent/KR0126886B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 높은 단차와 높은 반사율을 갖는 전도층 지역 쪽의 홀의 사이즈는 원하는 사이즈 보다 적게 디자인하고, 낮은 단차와 낮은 반사율을 갖는 전도층 쪽의 홀 사이즈는 상대적으로 크게 디자인하되, 상기 두 전도층 경계지역은 정렬오차를 고려하여 낮은 단차와 낮은 반사율을 갖는 전도층 쪽의 홀 사이즈를 높은 단차와 높은 반사율을 갖는 전도층 지역 쪽으로 연장하여 디자인 하는 것을 특징으로 하는 버팅 콘택 마스크 디자인 방법에 관한 것으로, 접속되는 두 전도층의 접촉저항이 동일한 버팅 비아 홀을 형성하여 소자의 신뢰도 및 수율을 향상시키는 효과가 있다.According to the present invention, the size of the hole toward the conductive layer region having high step height and high reflectance is designed to be smaller than the desired size, and the size of the hole on the conductive layer side having low step height and low reflectance is relatively large, but the boundary between the two conductive layer is The region relates to a method of designing a butting contact mask, characterized by extending the hole size toward the conductive layer region having a high step height and a high reflectance in consideration of an alignment error. There is an effect of improving the reliability and yield of the device by forming a butting via hole of the same contact resistance of the two conductive layers.

Description

버팅 콘택 마스크 디자인 방법How to Design a Butting Contact Mask

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따른 버팅 콘택 마스크 디자인 방법을 나타내는 평면도,4 is a plan view showing a butt contact mask design method according to the present invention,

제5도는 본 발명에 의해 제작된 버팅 콘택 마스크를 사용하여 버팅 비아 홀을 형성한 상태의 웨이퍼 평면도.5 is a plan view of a wafer in which a butt via hole is formed using a butt contact mask fabricated according to the present invention.

Claims (1)

버팅 콘택 마스크 디자인 방법에 있어서, 높은 단차와 높은 반사율을 갖는 전도층 지역 쪽의 홀의 사이즈는 원하는 사이즈 보다 적게 디자인하고, 낮은 단차와 낮은 반사율을 갖는 전도층 쪽의 홀 사이즈는 상대적으로 크게 디자인하되, 상기 두 전도층 경계지역은 정렬오차를 고려하여 낮은 단차와 낮은 반사율을 갖는 전도층 쪽의 홀 사이즈를 높은 단차와 높은 반사율을 갖는 전도층 지역 쪽으로 연장하여 디자인하는 것을 특징으로 하는 버팅 콘택 마스크 디자인 방법.In the butting contact mask design method, the hole size toward the conductive layer area having high step height and high reflectance is designed to be smaller than the desired size, and the hole size toward the conductive layer having low step height and low reflectance is relatively large. Butting contact mask design method characterized in that the two conductive layer boundary region is designed to extend the hole size of the conductive layer having a low step and low reflectance toward the conductive layer area having a high step and high reflectance in consideration of alignment error . ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005777A 1994-03-22 1994-03-22 Contact mask design method KR0126886B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940005777A KR0126886B1 (en) 1994-03-22 1994-03-22 Contact mask design method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940005777A KR0126886B1 (en) 1994-03-22 1994-03-22 Contact mask design method

Publications (2)

Publication Number Publication Date
KR950027960A true KR950027960A (en) 1995-10-18
KR0126886B1 KR0126886B1 (en) 1998-04-02

Family

ID=19379401

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940005777A KR0126886B1 (en) 1994-03-22 1994-03-22 Contact mask design method

Country Status (1)

Country Link
KR (1) KR0126886B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102050958B1 (en) 2017-11-24 2019-12-03 문서윤 Folding billboard

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Publication number Publication date
KR0126886B1 (en) 1998-04-02

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