KR950026265A

KR950026265A - Memory controller and method for relocating image data

Info

Publication number: KR950026265A
Application number: KR1019940002413A
Authority: KR
Inventors: 이상락
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1994-02-08
Filing date: 1994-02-08
Publication date: 1995-09-18
Also published as: KR100209875B1

Abstract

본 발명은 영상데이타를 압축 및 부호화하여 기록하는 시스템에서 압축시 변형된 영상데이타의 배열을 간단한 구성에 의해 다시 재배열하도록 한 영상데이타의 재배치를 위한 메모리 제어장치 및 그 방법에 관한 것이다. 이러한 본 발명은 데이타 압축부와 에러정정 외부호화부 사이에 데이타 재배열부를 구비한다. 상기 데이타 재배열부는 압축된 영상데이타를 교대로 기록/판독하는 메모리부와, 메모리부의 입출력단에서 전송된 영상 데이타를 래치하는 입력래치부 및 출력래치부를 구비한다. 아울러 현재 입력되는 영상데이타에 관한 정보를 메모리제어부에 알려주는 타이밍발생부와, 메모리부의 기록/판독동작을 제어하는데 필요한 각종 신호를 만들어 출력하는 메모리 제어부를 구비한다. 상기 메모리제어부는 영상데이타를 외부호길이만큼 어드레스의 간격을 두고 메모리에 기록하고, 설정된 갯수의 매크로블럭이 입력될때마다 상기 어드레스에 각각 1씩 오프셋 이 가해진 상태로 메모리에 기록한다. 그러나 판독시에는 어드레스를 순차적으로 1씩 증가시키면서 메모리에 있는 데이타를 직렬로 독출하게 된다.The present invention relates to a memory control apparatus and method for rearranging image data in which a system for compressing, encoding, and recording image data is rearranged again by a simple configuration. The present invention includes a data rearrangement unit between the data compression unit and the error correction outer coder. The data rearrangement unit includes a memory unit for alternately writing / reading compressed image data, an input latch unit and an output latch unit for latching image data transmitted from an input / output terminal of the memory unit. In addition, it comprises a timing generator for notifying the memory controller of information about the currently input image data, and a memory controller for generating and outputting various signals necessary for controlling the write / read operation of the memory unit. The memory controller writes the image data into the memory at the address interval by the external call length, and writes the image data into the memory with an offset applied to each of the addresses each time a predetermined number of macroblocks are input. When reading, however, the data in the memory is read in serial while the address is sequentially increased by one.

Description

Memory controller and method for relocating image data

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 디지탈 VCR 시스템의 개략구성을 나타낸 블럭도,3 is a block diagram showing a schematic configuration of a digital VCR system of the present invention;

제4도는 영상데이타의 압축단위를 나타낸 화면상태도.4 is a screen state diagram showing a compression unit of image data.

Claims

An apparatus for compressing and encoding sampled image data and recording the same on a medium, comprising: a memory unit for storing compressed image data according to a control signal and an address signal applied from a memory controller and outputting the stored data; An input latch unit for latching and outputting image data compressed and transmitted according to an output enable signal applied from the memory controller; An output latch unit for outputting the image data read out from the memory unit in accordance with an output enable signal applied from the memory controller; A timing generator for generating and outputting a global timing signal for informing information about image data currently input to the memory unit; And a memory control unit configured to receive the global timing signal and control the write / read operation of the memory unit and output the signals to the memory unit, the input latch unit, and the output latch unit, respectively. Memory controller.

2. The relocation of video data according to claim 1, wherein the memory unit comprises two memories which perform a read operation when one memory performs a write operation and alternately perform a read operation and perform a write / read operation in units of frames. Memory controller for

The method of claim 1, wherein the global timing signal output from the timing generator is a signal indicating that a macroblock of a predetermined number is input, a signal indicating that a frame is changed, and whether the frame is an odd frame or an even frame. Memory control device for repositioning the image data, characterized in that it comprises a signal to tell.

The control signal output from the memory controller is a signal for determining a write / read mode of the two memories, a chip select signal of the two memories, and write and read data at predetermined positions of the two memories. And an output enable signal for controlling the input latch unit and the output latch unit, respectively.

An apparatus for compressing and encoding sampled image data and recording on a medium, comprising: a data compression step of compressing the sampled image data in macroblock units according to a predetermined ratio; A data rearrangement step of rearranging the arrangement of the deformed image data upon compression by designating different addresses at the time of recording and reading; And an error correction external encoding step of encoding by adding an external code bit for correcting a cluster error to the rearranged image data.

The method of claim 5, wherein the rearranging of the data comprises: recording image data input in units of macroblocks at an address interval corresponding to an external call length; Recording data with an offset applied to the recording address by 1 each time a predetermined number of macroblocks are input; And reading out the serially written data while sequentially increasing the address by one during reading.

6. The method of claim 5, wherein the rearranging of the data comprises: recording image data input in macroblock units in serial order by incrementing addresses by 1; Reading the recorded data with the address spaced apart by the external code length during reading; And reading out the recorded data with an offset applied to the read address by one each time a predetermined number of macroblocks are read out.

※ Note: The disclosure is based on the initial application.