KR100209875B1 - Memory control apparatus and method for reordering image data - Google Patents

Abstract

The present invention relates to a memory control apparatus and method for rearranging image data in which a system for compressing, encoding, and recording image data is rearranged again by a simple configuration. The present invention includes a data rearrangement unit between the data compression unit and the error correction outer coder. The data rearrangement unit includes a memory unit for alternately writing / reading compressed image data, an input latch unit and an output latch unit for latching image data transmitted from an input / output terminal of the memory unit. In addition, a timing generation unit for notifying the memory controller of information about the currently input image data, and a memory control unit for generating and outputting various signals necessary for controlling the write / read operation of the memory unit. The memory controller writes the image data into the memory at intervals of an address by the length of an external code, and writes the data into the memory with an offset of one address each time the set number of macroblocks is input. When reading, however, the data in the memory is read in serial while the address is sequentially increased by one.

Description

Memory controller and method for relocating image data

1 is a block diagram showing a schematic configuration of a conventional digital VCR system.

(A) and (b) of FIG. 2 are diagrams of arrangement of image data before and after encoding, and a flow of recording and reading of data for encoding.

3 is a block diagram showing a schematic configuration of a digital VCR system of the present invention.

4 is a screen state diagram showing a compression unit of image data.

5 is a data format state after image data compression.

6 is a flowchart for recording and reading data for encoding.

7 is a block diagram showing the detailed configuration of the data rearrangement in FIG.

8 is a memory map showing the arrangement of data written and read for relocation.

9 is a state diagram for explaining a process in which data is arranged by writing / reading of a memory.

(A)-(b) of FIG. 10 are the input / output waveforms of each part of FIG.

* Explanation of symbols for main parts of the drawings

40: error correction external encoder 50: interleaver

60: error correction internal encoding unit 110: data storage unit

120: data rearrangement unit 121: memory unit

122: input latch part 123: output latch part

124: timing generator 125: memory controller

MEM1, MEM2: Memory LAT1-LAT4: Latch

The present invention relates to a memory device for rearranging image data in a system for encoding and recording or transmitting a video signal. In particular, when the image data is compressed, an arrangement of the deformed image data during compression before the error correction encoding is performed at a later stage thereof. The present invention relates to a memory control apparatus for rearranging image data and to a method for transforming the image data by a simple configuration.

In addition to the development of broadcast digital VCRs, the development of consumer digital VCRs is in full swing. Digital VCRs such as D-2 and D-3 process video data without compression in order to prevent image deterioration during repeated dubbing and trick play. However, in the consumer digital VCR, data compression is performed on source data in order to increase the recording density of the tape. Compression method of image data collects data that spans multiple lines to form one compression block, that is, macroblock, and then collects several macroblocks and fixes fixed length in cluster unit. There is a way to make it. When such data compression is performed during image signal processing, the arrangement of the image data is deformed. In order to process the data at the rear end of the data compression unit, the arrangement of the image data must be modified again.

1 is a block diagram showing a schematic configuration of a conventional digital VCR system that does not compress video data. As shown, an analog / digital converter 10 for sampling and converting an analog video signal into a digital signal is connected to the channel separator 20, and the channel separator 20 is configured in units of input frames or fields. Image data can be divided into several time bands and processed in parallel. The shuffling unit 30 is connected to an output terminal of the channel separator 20 so that the image data is mixed with each other by a predetermined rule so that the error is not concentrated, and the image data output from the shuffling unit 30 is error corrected. It is applied to an Error Correction Outer Coding (40).

The error correction external encoder 40 adds and encodes an external code bit for correcting a cluster error to the input image data, and the image data encoded by the interleaver 50 connected to the output terminal of the error correction external encoder 40. Randomly shuffle and print An error correction inner coding unit 60 is connected to an output terminal of the interleaver 50 so as to encode an internal code bit for correcting an irregular error in image data. The synchronization unit 70 connected to the output terminal of the error correction internal encoder 60 adds and outputs a synchronization signal to the encoded image data, and applies the output data to the modulation unit 80 to modulate the carrier wave. The parallel-to-serial converter 90 connected to the output terminal of the modulator 80 converts the image data inputted in the parallel data form into the serial data form and outputs it to the write lamp 100, and the record equalizer 100 The frequency characteristics of the image data changed in the above-described signal processing are compensated for and output to the recording head.

When the analog video signal is input to the conventional digital VCR system configured as described above, the analog / digital converter 10 samples the signal and outputs the digital video data, and the channel separator 20 controls the frame so that the data rate is not high. In addition, the image data input in field units is separated into several bands and output to the shuffling unit 30. Here, shuffling means mixing the image data with a certain rule within a certain range (eg, a field), and the purpose of shuffling is to be displayed in the displayed screen even if error correction is not successful due to error truncation coding at a later stage. This is to distribute the error so that the pixel in which the error occurs is not concentrated. The image data output from the shuffling unit 30 is applied to the error correction external encoder 40 to add an external code bit.

2 is a state diagram showing the state of image data arrangement before and after error correction external encoding and the recording and reading flow of data for encoding. (A) of FIG. 2 shows the arrangement state of the image data after being shuffled. The number on the vertical axis indicates the line number, and the number on the horizontal axis indicates the pixel number in one scanning line. This can be one frame or one field. As shown in (a) of FIG. 2, the image data that is shuffled into the memory of the error correction external encoder 40 is mixed with each other in the line as shown in (b) of FIG. As shown, each line is written in series. When all the shuffled video data enters the memory, the external code parity bits are sequentially added and read in the direction of the arrow as in recording. Therefore, there is no need to rearrange any data for error correction external encoding.

The video data primarily encoded by the error correction external encoder 40 is applied to the interleaver 50 and randomly mixed and output. The data output from the interleaver 50 is applied to the error correction internal coder 60 and encoded second by adding an internal code parity bit, and the encoded image data is applied to the synchronization adder 70 to provide an existing video signal. A synchronization signal different from the synchronization signal included in is added. Data output from the synchronization unit 70 is applied to the modulation unit 80 to modulate a carrier wave, and the modulated video signal is converted into serial data by the parallel-to-serial conversion unit 90, and then the record equalizer. The frequency characteristic is compensated for by 100 and recorded on the tape through the head.

However, this conventional method is applied when the image data is not compressed. When the image data is compressed, the data is transmitted in units of macroblocks, so that the arrangement of the image data is modified so that error correction coding and other signal processing are performed at the back stage. In order to do this, there is a problem of re-arranged the compressed image data.

The present invention is to solve the above-mentioned problems, the object of the present invention is to rearrange the arrangement of the modified image data during compression in a system for compressing and recording the image data by a simple configuration to correct the error at the rear end The present invention provides a memory control apparatus and method for relocating image data to facilitate code and other signal processing.

Memory control apparatus for rearranging the image data of the present invention for achieving the above object is a data compression unit for compressing and outputting the input image data; An input latch unit for latching and outputting image data inputted from the data compression unit, a memory unit for storing and outputting the image data inputted from the input latch unit at a different address during writing and reading, and an image from the memory unit. An output latch unit for receiving and outputting data, a timing generator for generating and outputting a global timing signal related to image data currently input to the memory unit, and a block for controlling the write / read operation of the memory unit for receiving the global timing signal. A data rearrangement unit configured of a memory control unit for controlling the control unit; And an error correction encoding unit for encoding by adding an external encoding bit for correcting the cluster error to the image data input from the output latch unit.

In addition, the memory control method for relocating the image data of the present invention for achieving the above object comprises a data compression step of compressing the sampled image data in macroblock units according to a predetermined ratio; Data reordering step of rearranging the arrangement of the deformed image data when compressing by designating different addresses at the time of recording and reading: and encoding by adding external code bits to correct the cluster error in the rearranged image data An error correction outer coding step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 10.

3 is a block diagram showing a schematic configuration of a digital VCR system of the present invention employing a video data compression method. As shown, an analog / digital converter 10 for sampling and converting an analog video signal into a digital signal is connected to the channel separator 20, and the channel separator 20 is configured in units of input frames or fields. Image data can be divided into several time bands and processed in parallel. The data compression unit 110 is connected to an output terminal of the channel separator 20 to compress the image data in macroblock units according to a predetermined ratio, and the image data output from the data compression unit 110 is the data rearrangement unit 120. Is applied.

The data rearranging unit 120, which is a feature of the present invention, rearranges the modified image data when compressed by the data compression unit 110 by designating different addresses at the time of recording and reading. The image data output from the column unit 120 is applied to the error correction external encoder 40. The error correction external encoder 40 adds and encodes an external code bit for correcting a cluster error to the input image data, and the image data encoded by the interleaver 50 connected to the output terminal of the error correction external encoder 40. Prints randomly. An error correction internal coder 60 is connected to an output terminal of the interleaver 50 to add and encode an internal code bit for correcting an irregular error in the image data. The synchronization unit 70 connected to the output terminal of the error correction internal encoder 60 adds and outputs a synchronization signal to the encoded image data, and the output data is applied to the modulation unit 80 to modulate the carrier wave. The parallel-serial converter 90 connected to the output terminal of the modulator 80 converts the image data input in the parallel data form into the serial data form and outputs the serial data to the record equalizer 100. The record equalizer 100 The frequency characteristics of the image data changed in the above-described signal processing are compensated for and output to the recording head.

When the analog video signal is input to the system of the present invention configured as described above, the analog-digital converter 10 samples the signal and outputs the digital video data, and the channel separator 20 does not frame the data rate so that the data rate is not high. In addition, the image data input in field units is divided into several bands and outputted to the data compression unit 110. Here, systems that apply data compression typically do not shuffle. The reason for this is that shuffling means random mixing of the image data. When the data is mixed like this, the correlation between the image data is lowered, and the lack of correlation means that the compression is difficult.

4 is a screen state diagram showing a unit of compressing image data, and shows a unit of compression of a luminance signal and a color difference signal having a data compression ratio of 4: 2: 2. In order to encode the image data, the screen is divided into blocks having a predetermined size. In FIG. 4, a block indicated by hatching is a macro block (MB) indicating a minimum unit for compressing the image data. When the data compression ratio is 4: 2: 2, the luminance signal Y is 16x16 = 256 pixels as shown in (a) of FIG. 4, and the chrominance signal RY (BY) as shown in (a) (c) of FIG. Each has 8 x 16 = 128 pixels to form one macroblock. The data compression rate is determined according to the system specification (SPEC). If compression is 4: 1, the total data amount of one macroblock before compression is 256 + 128 + 128 = 512 bytes, which is 512/4 = 128 bytes. When the image data is compressed in this manner, the previous line and pixel concepts are lost, so all data are processed in macroblock units, and subsequent processing must maintain the data in macroblock units.

5 shows a data format state after compressing image data. As shown, the image data is composed of macroblock units, and the number of macroblocks varies according to the specification of the system. Since m and n are integers, the number of macroblocks is present in integer units within 1 field and 1 frame. do. Here, the macroblock, which is the compression unit of the image data, is related to the internal code used for error correction encoding. It is for playing data.

FIG. 6 is a state diagram showing a procedure of writing and reading the compressed image data as described above into a memory for error correction external encoding. As described above, the macroblock is a unit of error correction internal encoding, and therefore, the macroblock should be written in the memory in consideration of this. The arrow A in the horizontal direction is the recording direction of the image data coming from the data compression unit 110, and becomes the direction of error correction internal encoding, and the arrow B in the vertical direction is the image data in the memory for error correction external encoding. Is the direction to read. As described above, the compressed image data has different error correction internal encoding in units of macroblocks, and thus the recording direction of the image data coming from the data compression unit 110 is different from the reading direction read from the memory for error correction external encoding. The length of the vertical axis is equal to the length of the outer code (Outer Code Length), and the number of macroblocks that can enter the horizontal direction is determined accordingly. The size of the macroblock depends on the degree of compression. If the size of the macroblock is | c│ and the total number of macroblocks that can fit into n is n, the error correction outer coding is performed again. There is a need for a read / write memory for transforming into an arrangement for performing and a controller for controlling the same.

FIG. 7 is a block diagram showing a detailed configuration of the data rearrangement unit 120 in FIG. 3. The data rearrangement unit of the present invention compresses image data compressed according to a control signal and an address signal applied from the memory controller 125. And a memory section 121 for storing and outputting the stored data. The memory section 121 is composed of two memories MEM MEM which alternately perform writing / reading operations. An input latch unit 122 including two latches LAT1 and LAT2 is connected to an input terminal of the memory unit 121, and the input latch unit 122 is an output enable signal applied from the memory controller 125. According to (OE), the image data transmitted from the data compression unit 110 is latched and output to the memory unit 121. An output latch 123 composed of two latches LAT3 and LAT4 is connected to an output terminal of the memory unit 121, and the output latch unit 123 is an output enable signal applied from the memory controller 125. According to (OE), the image data read out from the memory unit 121 is output to the error correction external encoder 40.

In addition, the data rearrangement unit of the present invention includes a timing generation unit 124 for generating and outputting a global timing signal informing the information on the image data currently input. A memory controller 125 is connected to an output terminal of the timing generator 124, and the memory controller 125 receives the global timing signal and receives various signals necessary to control the write / read operation of the memory 121. It is made to output to the memory unit 121, the input latch unit 122 and the output latch unit 123.

The operation of the data rearrangement unit configured as described above will be described based on the waveform diagram of FIG.

First, the timing generator 124 synchronizes with the clock signal clk as shown in (a) of FIG. 10 in order to inform the memory controller 125 of information about the image data currently input from the data compressor 110. Create and output global timing signals (macro_n, f_rst, oe_frame). As shown in FIG. 10, macro_n is a signal inputted in units of n macroblocks, and as shown in (b) of FIG. 10, f_rst is a signal for notifying each time a frame is changed. oe_frame is a signal indicating whether a frame is an odd frame or an even frame, as shown in ⒞ of FIG. 10. The oe_frame is a signal required to alternately use two memories MEM1 and MEM2 for reading and writing for each frame. If this signal is low potential, it is an odd frame, and if it is high potential, it is an even frame.

The global timing signal output from the timing generator 1240 is applied to the memory controller 125, and the memory controller 125 generates signals necessary for controlling the write / read operation of the memory 121 using this signal. When the signals of the memory controller 125 are described, M0_OE, M1_OE, M0_WE, and M1_WE (see FIG. 10) refer to the modes (read / write) of the two memories MEM1 and MEM2 of the memory unit 121. M0_CS and M1_CS are chip select signals of two memories (MEM). When one memory performs a write operation by these signals, the other memory simultaneously M0_ADDR and M1_ADDR represent the addresses of two memories MEM1 and MEM2, respectively, and M0_WRITE and M1_WRITE (see FIG. 10) control the input latch 122, and M0_READ and M1_READ. (See FIG. 10) controls the output latch unit 123.

8 is a memory map showing a data arrangement state for one channel and one frame that is recorded and read out in the memory unit of the present invention to rearrange video data. The arrow A in the horizontal direction is a direction for writing image data in the memory, and the arrow B in the vertical direction is a direction for reading image data in the memory. The length of the vertical axis is equal to the length of the outer arc (ocl), the size of the macroblock is | c | bytes, and the number of macroblocks entering the horizontal direction is n.

FIG. 9 is a state diagram for explaining the process of actually arranging the data in the memory by the write / read operation of the memory. As shown in FIG. 9, when the data of the internal code block in macroblock units inputted from the data compression unit 110 are read into the memory in order to read out the necessary external code block OBC from the memory in series. As shown, when data of one macroblock MB1 composed of | c | bytes comes in, each of the data is written to the memory at an address interval by the outer code length (ocl). That is, as shown in FIG. 10, the video data of MB1 is recorded at addresses of 0, ocl, 2 * ocl, 3 * ocl, and so on. When the macro_n signal is inputted from the timing generator 1240 in this order, subsequent data of " c | * n bytes from MBn + 1 to MB2n are written to the memory with an offset of 1 each. , 1, ocl + 1, 2 * ocl + 1, 3 * ocl + 1, etc. When macro_n signal is input again, 2, ocl + 2, 2 * ocl + 2, 3 * ocl + When recording is performed at an address such as 3, and the like is continuously recorded in this manner, and the oe_frame signal and the f_rst signal are input from the timing generator 124, the two memories MEM1 and MEM2 switch roles of reading and writing. At this time, the write and read addresses are set to zero, which is an initial value.

In fact, there are two ways to implement the memory mapping state as shown in FIG. One is to read and write data serially when writing and reading as above. The other is to read and write data as above when writing and reading data serially when writing. As a method, the two methods are the same for controlling the memory. In the first method, a read address for simply reading data serially may read the data in the memory while sequentially increasing by 1, as shown in FIG.

As described above, the data rearrangement unit 120 rearranges the deformed image data during compression by designating different addresses at the time of recording and reading, and then outputs the image data output from the data rearrangement unit 120 to correct the error. Applied to the unit 40, an external code bit is added. The video data encoded by the error correction external encoder 40 of FIG. 3 is applied to the interleaver 50 and randomly shuffled. The data output from the interleaver 50 is applied to the error correction internal coder 60 and encoded second by adding an internal code parity bit, and the encoded image data is applied to the synchronization adder 70 to provide an existing video signal. A synchronization signal different from the synchronization signal included in is added. Data output from the synchronization unit 70 is applied to the modulation unit 80 to modulate a carrier wave, and the modulated video signal is converted into serial data by the parallel-to-serial conversion unit 90, and then the record equalizer. The frequency characteristic is compensated for by 100 and recorded on the tape through the head.

As described above, the present invention reorders the modified image data upon compression by a simple configuration by designating different addresses at the time of recording and reading using a memory device in a system for compressing and recording the image data. It is effective to facilitate error correction coding and other signal processing at the end of the subject.

Claims (4)

An apparatus for compressing and encoding sampled image data and recording the same on a medium, the apparatus comprising: a data compression unit configured to compress and output input image data; An input latch unit for latching and outputting image data input from the data compression unit, a memory unit for storing and outputting the image data input from the input latch unit at different writing and reading times, and the memory unit An output latch unit for receiving and outputting image data from the image output unit, a timing generator for generating and outputting a global timing signal related to the image data currently input to the memory unit, and receiving the global timing signal for recording / reading operation of the memory unit. A data rearrangement unit configured of a memory control unit controlling each block to control the block; And an error correction external encoding unit configured to add and encode an external encoding bit for correcting a cluster error to the image data inputted from the output latch unit. 2. The relocation of video data according to claim 1, wherein the memory unit comprises two memories which perform a read operation when one memory performs a write operation and alternately perform a read operation and perform a write / read operation in units of frames. Memory controller for The method of claim 1, wherein the global timing signal output from the timing generator is a signal indicating that a predetermined number of macroblocks are input, a signal indicating that a frame is changed, and whether the frame is an odd frame or an even frame. Memory control device for repositioning the image data, characterized in that it comprises a signal to tell. A method for compressing and encoding sampled image data and recording the same on a medium, the method comprising: compressing sampled image data in macroblock units according to a predetermined ratio; A data rearrangement step of rearranging the arrangement of the deformed image data upon compression by designating different addresses at the time of recording and reading; And an error correction outer encoding step of encoding and adding an outer code bit for correcting a cluster error to the rearranged image data.