KR950025784A - Cell Data Output Circuit of Semiconductor Memory - Google Patents
Cell Data Output Circuit of Semiconductor Memory Download PDFInfo
- Publication number
- KR950025784A KR950025784A KR1019940003087A KR19940003087A KR950025784A KR 950025784 A KR950025784 A KR 950025784A KR 1019940003087 A KR1019940003087 A KR 1019940003087A KR 19940003087 A KR19940003087 A KR 19940003087A KR 950025784 A KR950025784 A KR 950025784A
- Authority
- KR
- South Korea
- Prior art keywords
- pull
- sense amplifier
- data
- circuit
- line
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Dram (AREA)
Abstract
반도체 기억장치의 셀 어레이 연결된 센스증폭기의 풀다운센스증폭회로가 데이타 버스라인에 대해 구성한 풀업 센스증폭회로와 동작하도록 하여 데이타 버스의 로딩팩터(loading factor)가 커져 발생하는 신호지연요소를 개선하도록 하고 데이타 전송이 신뢰성있게 이루어지도록 반도체 기억장치의 셀어레이의 셀데이타를 인출하기 위한 데이타 출력회로로서, 상기 셀 어레이이의 셀 비트라인에 연결되는 풀업 및 풀다운 센스 증폭회로로 구성된 센스 증폭기와, 풀업 센스 증폭회로 및 풀다운 센스 증폭회로를 연결하는 비트라인에 연결한 데이타 버스라인과, 상기 데이타 버스라인의 충전 등화를 위한 라인간 연결된 충전등화수단 및 풀업센싱을 위한 데이타라인 풀업센스회로와, 비트라인측에 연결된 데이타 라인 충전등화 및 풀업센스회로간에 연결된 스위칭수단으로 구성된다.The pull-down sense amplifier circuit of the sense amplifier connected to the cell array of the semiconductor memory device operates with the pull-up sense amplifier circuit configured for the data bus line to improve the signal delay factor caused by the increase in the loading factor of the data bus. A data output circuit for extracting cell data of a cell array of a semiconductor memory device for reliable transmission, comprising: a sense amplifier comprising a pull-up and pull-down sense amplifier circuit connected to a cell bit line of the cell array; and a pull-up sense amplifier circuit. And a data bus line connected to a bit line connecting the pull down sense amplification circuit, a charge equalization means connected between lines for charge equalization of the data bus line, a data line pull up sense circuit for pull up sensing, and a bit line side. Connected between data line charge equalization and pull-up sense circuits It consists of a switching means.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명에 따른 반도체 기억장치의 셀 데이타 출력 회로도.3 is a cell data output circuit diagram of a semiconductor memory device according to the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003087A KR960009957B1 (en) | 1994-02-22 | 1994-02-22 | Cell data output circuit of semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003087A KR960009957B1 (en) | 1994-02-22 | 1994-02-22 | Cell data output circuit of semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950025784A true KR950025784A (en) | 1995-09-18 |
KR960009957B1 KR960009957B1 (en) | 1996-07-25 |
Family
ID=19377524
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940003087A KR960009957B1 (en) | 1994-02-22 | 1994-02-22 | Cell data output circuit of semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR960009957B1 (en) |
-
1994
- 1994-02-22 KR KR1019940003087A patent/KR960009957B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR960009957B1 (en) | 1996-07-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR930003153A (en) | Semiconductor integrated circuit device | |
KR930001226A (en) | Sense Amplifiers Perform High-Speed Sensing Operations | |
KR890016471A (en) | Data output buffer circuit in semiconductor device | |
KR890010909A (en) | Semiconductor memory circuit | |
KR880010422A (en) | Semiconductor memory | |
KR860004409A (en) | Semiconductor memory | |
KR910010506A (en) | Semiconductor devices | |
KR880004478A (en) | Semiconductor memory | |
KR930018582A (en) | Bit Line Separation Clock Generator in Semiconductor Memory Devices | |
KR960025791A (en) | Sense amplifier circuit | |
KR930001229A (en) | Semiconductor memory device | |
KR910010530A (en) | High speed recording circuit in RAM test | |
KR900019041A (en) | Semiconductor memory | |
KR960025011A (en) | Data input / output detection circuit of memory device | |
KR950025784A (en) | Cell Data Output Circuit of Semiconductor Memory | |
KR960027317A (en) | Data Output Buffer Circuit of Semiconductor Memory Device | |
KR940001149A (en) | Semiconductor memory | |
KR920022300A (en) | Semiconductor memory device with improved write operation | |
KR910010513A (en) | Dynamic RAM Separation Circuit | |
KR910017423A (en) | Semiconductor memory device | |
KR900000902A (en) | Dynamic RAM | |
EP0791931A3 (en) | Semiconductor memory device | |
KR970051112A (en) | Sink RAM with Dual Output Ports | |
KR950009070B1 (en) | Control signal gnable circuit | |
KR940016252A (en) | Effective Sensing Margin Circuit During Short Equalizing Time |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20100624 Year of fee payment: 15 |
|
LAPS | Lapse due to unpaid annual fee |