KR950025784A - Cell Data Output Circuit of Semiconductor Memory - Google Patents

Cell Data Output Circuit of Semiconductor Memory Download PDF

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Publication number
KR950025784A
KR950025784A KR1019940003087A KR19940003087A KR950025784A KR 950025784 A KR950025784 A KR 950025784A KR 1019940003087 A KR1019940003087 A KR 1019940003087A KR 19940003087 A KR19940003087 A KR 19940003087A KR 950025784 A KR950025784 A KR 950025784A
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KR
South Korea
Prior art keywords
pull
sense amplifier
data
circuit
line
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KR1019940003087A
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Korean (ko)
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KR960009957B1 (en
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정원화
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문정환
금성일렉트론 주식회사
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Priority to KR1019940003087A priority Critical patent/KR960009957B1/en
Publication of KR950025784A publication Critical patent/KR950025784A/en
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Publication of KR960009957B1 publication Critical patent/KR960009957B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • Dram (AREA)

Abstract

반도체 기억장치의 셀 어레이 연결된 센스증폭기의 풀다운센스증폭회로가 데이타 버스라인에 대해 구성한 풀업 센스증폭회로와 동작하도록 하여 데이타 버스의 로딩팩터(loading factor)가 커져 발생하는 신호지연요소를 개선하도록 하고 데이타 전송이 신뢰성있게 이루어지도록 반도체 기억장치의 셀어레이의 셀데이타를 인출하기 위한 데이타 출력회로로서, 상기 셀 어레이이의 셀 비트라인에 연결되는 풀업 및 풀다운 센스 증폭회로로 구성된 센스 증폭기와, 풀업 센스 증폭회로 및 풀다운 센스 증폭회로를 연결하는 비트라인에 연결한 데이타 버스라인과, 상기 데이타 버스라인의 충전 등화를 위한 라인간 연결된 충전등화수단 및 풀업센싱을 위한 데이타라인 풀업센스회로와, 비트라인측에 연결된 데이타 라인 충전등화 및 풀업센스회로간에 연결된 스위칭수단으로 구성된다.The pull-down sense amplifier circuit of the sense amplifier connected to the cell array of the semiconductor memory device operates with the pull-up sense amplifier circuit configured for the data bus line to improve the signal delay factor caused by the increase in the loading factor of the data bus. A data output circuit for extracting cell data of a cell array of a semiconductor memory device for reliable transmission, comprising: a sense amplifier comprising a pull-up and pull-down sense amplifier circuit connected to a cell bit line of the cell array; and a pull-up sense amplifier circuit. And a data bus line connected to a bit line connecting the pull down sense amplification circuit, a charge equalization means connected between lines for charge equalization of the data bus line, a data line pull up sense circuit for pull up sensing, and a bit line side. Connected between data line charge equalization and pull-up sense circuits It consists of a switching means.

Description

반도체 기억장치의 셀 데이타 출력 회로Cell Data Output Circuit of Semiconductor Memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 반도체 기억장치의 셀 데이타 출력 회로도.3 is a cell data output circuit diagram of a semiconductor memory device according to the present invention.

Claims (4)

반도체 기억장치의 셀어레이의 셀데이타를 인출하기 위한 데이타 출력 회로로서, 상기 셀 어레이이의 셀 비트라인에 연결되는 풀업 및 풀다운 센스 증폭회로로 구성된 센스증폭기와, 풀업 센스 증폭회로 및 풀다운 센스 증폭회로를 연결하는 비트라인에 연결한 데이타 버스라인과, 상기 데이타 버스라인의 충전등화를 위한 라인간 연결된 충전등화수단 및 풀업센싱을 위한 데이타라인 풀업센스회로와, 비트라인측에 연결된 데이타 라인과 데이타 라인 충전등화 및 풀업센스회로간에 연결된 스위칭수단으로 구성된 것을 특징으로 하는 반도체 기억장치의 셀 데이타 출력 회로.A data output circuit for extracting cell data of a cell array of a semiconductor memory device, comprising: a sense amplifier comprising a pull-up and pull-down sense amplifier circuit connected to a cell bit line of the cell array, and a pull-up sense amplifier circuit and a pull-down sense amplifier circuit. A data bus line connected to a bit line to be connected, a charge equalization means connected between lines for charge equalization of the data bus line, a data line pull up sense circuit for pull-up sensing, and a data line and a data line charge connected to the bit line side A cell data output circuit of a semiconductor memory device, characterized by comprising switching means connected between equalization and pull-up sense circuits. 제1항에 있어서, 셀데이타가 비트라인에 전송되고 스위칭 수단의 턴온에 의해서 센스증폭기의 풀다운 센스증폭회로와 데이타라인의 풀업센스증폭회로가 하나의 센스증폭기를 형성하여 데이타를 인출하는 것을 특징으로 하는 반도체 기억장치의 셀 데이타 출력 회로.The method of claim 1, wherein the cell data is transmitted to the bit line and the pull-down sense amplifier circuit of the sense amplifier and the pull-up sense amplifier circuit of the data line form one sense amplifier and draw out data by turning on the switching means. A cell data output circuit of a semiconductor memory device. 제1항에 있어서, 상기 센스증폭기의 풀업 센스증폭회로와 풀다운 센스 증폭회로를 연결하는 비트라인에 셀 어레이 선택을 위한 스위칭수단을 포함하여 상기 데이타라인의 스위칭수단의 턴온싯점에서 스위칭오프되어 풀업센스 증폭회로와 풀다운 센스 증폭회로를 분리시키는 것을 특징으로 하는 반도체 기억장치의 셀 데이타 출력 회로.2. The apparatus of claim 1, further comprising a switching means for selecting a cell array in a bit line connecting the pull-up sense amplifier circuit and the pull-down sense amplifier circuit of the sense amplifier to be switched off at a turn-on point of the switching means of the data line. A cell data output circuit of a semiconductor memory device, characterized in that the amplifier circuit and the pull-down sense amplifier circuit are separated. 제1항에 있어서, 상기 인출된 데이타버스라인의 데이타는 데이타 버스 센스증폭기와 데이타출력버퍼를 통해 출력되도록 상기 구성을 더욱 포함하는 것을 특징으로 하는 반도체 기억장치의 셀 데이타 출력회로.2. The cell data output circuit of claim 1, further comprising the configuration such that the data of the extracted data bus line is output through a data bus sense amplifier and a data output buffer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940003087A 1994-02-22 1994-02-22 Cell data output circuit of semiconductor memory device KR960009957B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940003087A KR960009957B1 (en) 1994-02-22 1994-02-22 Cell data output circuit of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940003087A KR960009957B1 (en) 1994-02-22 1994-02-22 Cell data output circuit of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR950025784A true KR950025784A (en) 1995-09-18
KR960009957B1 KR960009957B1 (en) 1996-07-25

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KR1019940003087A KR960009957B1 (en) 1994-02-22 1994-02-22 Cell data output circuit of semiconductor memory device

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KR960009957B1 (en) 1996-07-25

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