KR950024573A - Station discrete cosine converter - Google Patents

Station discrete cosine converter Download PDF

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Publication number
KR950024573A
KR950024573A KR1019940000744A KR19940000744A KR950024573A KR 950024573 A KR950024573 A KR 950024573A KR 1019940000744 A KR1019940000744 A KR 1019940000744A KR 19940000744 A KR19940000744 A KR 19940000744A KR 950024573 A KR950024573 A KR 950024573A
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South Korea
Prior art keywords
multiplier
predetermined
discrete cosine
accumulator
inverse discrete
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KR1019940000744A
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Korean (ko)
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KR0122734B1 (en
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신헌기
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배순훈
대우전자 주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Discrete Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

본 발명은 역 이산 여현 변환 장치에 관한 것으로, 이러한 장치는 병렬로 소정기간동안 입력되는 데이타(X)와 종축으로 소정기간 소정횟수에 걸쳐 소정의 계수(C)를 승산하는 소정개의 승산기로 된 승산부와, 상기 승산부의 각각의 승산기의 승산 결과를 누적하고 소정기간 주기로 출력하는 소정개의 누산기로 된 누산부로 구성된 1차원 역 이산 여현 변환 수단과, 상기 1차원 역 이산 여현 변환 수단의 출력과 1T 주기로 입력되는 상기 계수(C)의 전치 행렬 계수(CT)를 승산하는 소정 개의 승산기로 된 승산부와, 상기 승산부의 출력을 소정 주기로 래치하는 디멀티플렉서와, 상기 디멀티플렉서의 출력을 누적하는 소정개의 누산기로 된 누산부와, 상기 누산부의 출력단에 연결되어 상기 누산부의 출력이 한 화소씩 출력되도록 하는 멀티플렉서로 구성된 2차원 역 이산 여현 변환 수단으로 이루어짐으로써, 전치용 램이 사용되지 않아 전체적으로 게이트 수가 줄어들시 회로 사이즈가 작아지고, 대기 시간이 줄어들어 회로 검토가 용이하게 된다.The present invention relates to an inverse discrete cosine converting apparatus, comprising: multiplying data (X) input in parallel for a predetermined period and a predetermined multiplier multiplying a predetermined coefficient (C) over a predetermined number of times for a predetermined period in the vertical axis. And a one-dimensional inverse discrete cosine converting means comprising an accumulating unit comprising a predetermined accumulator for accumulating the multiplication results of each multiplier of the multiplier and outputting the multiplier at a predetermined period. A multiplier comprising a predetermined multiplier for multiplying the transpose matrix coefficient C T of the input coefficient C, a demultiplexer for latching the output of the multiplier at a predetermined period, and a predetermined accumulator for accumulating the outputs of the demultiplexer. The secondary accumulator and a multiplexer connected to an output terminal of the accumulator and outputting the accumulator output one pixel at a time; As constituted by any inverse discrete cosine transform means, a ram for transposition not used as a whole is a circuit size smaller when lowering the number of gates, by reducing the waiting time is reviewed circuit is easy.

Description

역 이산 여현 변환 장치Station discrete cosine converter

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 1차원 역이산 여현 변환 장치를 나타낸 블럭도,2 is a block diagram showing a one-dimensional inverse discrete cosine transform device according to the present invention;

제3도는 제2도의 각 부의 동작을 나타낸 타이밍도.3 is a timing diagram showing the operation of each part of FIG.

Claims (3)

병렬로 소정기간동안 입력되는 데이타(X)와 종축으로 소정기간 소정횟수에 걸쳐 소정의 계수(C)를 승산하는 소정개의 승산기로 된 승산부와, 상기 승산부의 각각의 승산기의 승산 결과를 누적하고 소정기간 주기로 출력하는 소정개의 누산기로 된 누산부로 구성된 1차원 역 이산 여현 변환 수단과; 상기 1차원 역 이산 여현 변환 수단의 출력과 1T 주기로 입력되는 상기 계수(C)의 전치 행렬 계수(CT)를 승산하는 소정 개의 승산기로 된 승산부와, 상기 승산부의 출력을 소정 주기로 래치하는 디멀티플렉서와; 상기 디멀티플랙서의 출력을 누적하는 소정개의 누산기로 된 누산부와, 상기 누산부의 출력단에 연결되어 상기 누산부의 출력이 한 화소씩 출력되도록 하는 멀티플렉서로 구성된 2차원 역 이산 여현 변환 수단으로 이루어진 역 이산 여현 변환 장치.A multiplier comprising a multiplier that multiplies the data X input in parallel for a predetermined period and a predetermined coefficient C over a predetermined number of times in the vertical axis, and a multiplication result of each multiplier of the multiplier; One-dimensional inverse discrete cosine converting means consisting of an accumulating unit comprising a predetermined accumulator outputting at a predetermined period of time; A multiplier comprising a predetermined multiplier for multiplying the output of the one-dimensional inverse discrete cosine transforming means and the transpose matrix coefficient C T of the coefficient C input in a 1T period, and a demultiplexer for latching the output of the multiplier at a predetermined period. Wow; An inverse two-dimensional inverse discrete cosine converting means comprising an accumulator comprising a predetermined accumulator for accumulating the output of the demultiplexer and a multiplexer connected to an output of the accumulator and outputting the accumulator output one pixel at a time; Discrete cosine converter. 제1항에 있어서, 상기 1차원 역 이산 여현 변환 수단의 누산부는, 상기 각각의 승산기의 결과의 오차를 고러하여 상기 승산 결과에 클램핑 빛 라운딩을 하여 누적된 결과가 최대한 오차가 없도록 함을 특징으로 하는 역 이산 여현 변환 장치.The accumulating part of the one-dimensional inverse discrete cosine transform means is configured to clamp the light of the multiplication result by rounding the error of the result of each multiplier so that the accumulated result is not as large as possible. Inverse discrete cosine converter. 제1항에 있어서, 상기 디멀티플렉서의 전치 행렬 계수(CT)는 1T 쥐로 C0 C8 C16···C56의 순서로 승산부의 각각의 승산기로 입력됨을 특징으로 하는 역 이산 여현 변환 창치.The inverse discrete cosine transform window of claim 1, wherein the prematrix coefficients (C T ) of the demultiplexer are input to the respective multipliers of the multipliers in the order of C 0 C 8 C 16. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940000744A 1994-01-18 1994-01-18 Apparatus for inverse discrete cosine transform KR0122734B1 (en)

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KR1019940000744A KR0122734B1 (en) 1994-01-18 1994-01-18 Apparatus for inverse discrete cosine transform

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KR1019940000744A KR0122734B1 (en) 1994-01-18 1994-01-18 Apparatus for inverse discrete cosine transform

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KR950024573A true KR950024573A (en) 1995-08-21
KR0122734B1 KR0122734B1 (en) 1997-11-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030017251A (en) * 2001-08-24 2003-03-03 김희석 Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477203B1 (en) * 1998-10-30 2002-11-05 Agilent Technologies, Inc. Signal processing distributed arithmetic architecture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030017251A (en) * 2001-08-24 2003-03-03 김희석 Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition

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