KR20030017251A - Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition - Google Patents
Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition Download PDFInfo
- Publication number
- KR20030017251A KR20030017251A KR1020010051462A KR20010051462A KR20030017251A KR 20030017251 A KR20030017251 A KR 20030017251A KR 1020010051462 A KR1020010051462 A KR 1020010051462A KR 20010051462 A KR20010051462 A KR 20010051462A KR 20030017251 A KR20030017251 A KR 20030017251A
- Authority
- KR
- South Korea
- Prior art keywords
- idct
- dimensional
- dimensional idct
- row
- discrete cosine
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/625—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Discrete Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Compression Of Band Width Or Redundancy In Fax (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
Description
본 발명은 디지털 영상 신호 처리 방식 중 DCT/IDCT 기반 영상 신호 처리에서 DCT에 의해 압축된 영상을 복원하기 위한 2차원 IDCT 구조에 관한 것이다.The present invention relates to a two-dimensional IDCT structure for reconstructing an image compressed by DCT in DCT / IDCT based image signal processing among digital image signal processing methods.
최근 디지털 기술과 이에 따른 디지털 이동 통신의 기술이 발전함에 따라 멀티미디어에 대한 관심이 급증하고 있다. 특히 디지털 영상 데이터의 고속 전송에 관한필요성이 대두되므로서, 디지털 영상 신호에 대한 고속 압축 및 복원에 관한 기술적 연구가 활발하게 이루어지고 있으며, 그 결과로서 MPEG이라는 기술적 협의체가 구성되어 DCT/IDCT 기반의 영상 압축 방식을 채택하고 있다.Recently, with the development of digital technology and digital mobile communication technology, interest in multimedia is increasing rapidly. In particular, as the need for high-speed transmission of digital image data has emerged, technical research on high-speed compression and reconstruction of digital image signals has been actively conducted, and as a result, a technical consultation body called MPEG has been formed, which is based on DCT / IDCT. The video compression method is adopted.
종래의 행렬 분해형 2차원 IDCT 구조는 1개의 1차원 IDCT와 1개의 전치 메모리로 이루어진 형태(도2)와 2개의 1차원 IDCT와 1개의 전치 메모리를 이루어진 형태(도3)를 갖는다. 이러한 형태들의 구조는 1차원 IDCT 처리 후 전치 과정이 필요하므로 이로 인한 데이터 처리 병목 현상이 발생하며, 초기 지연 시간이 커진다. 또한 전치 메모리의 존재로 인한 면적이 커지는 단점이 있다.The conventional matrix decomposition type two-dimensional IDCT structure has a form consisting of one one-dimensional IDCT and one transpose memory (FIG. 2) and a form consisting of two one-dimensional IDCTs and one transposing memory (FIG. 3). Since the structures of these shapes require transposition after 1-dimensional IDCT processing, data processing bottlenecks occur and the initial delay time increases. In addition, there is a disadvantage that the area is increased due to the presence of the pre-memory memory.
본 발명은 행렬 분해형 2차원 IDCT로부터 전치과정을 제거하므로써, 회로 전체의 면적을 줄이고, 데이터 처리에 대한 초기 지연 시간을 줄이는데 그 목적이 있다.The present invention aims to reduce the area of the entire circuit and reduce the initial delay for data processing by eliminating the transposition process from the matrix decomposition type two-dimensional IDCT.
도 1은 본 발명에 따른 2차원 IDCT 구조도1 is a two-dimensional IDCT structure diagram according to the present invention
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1: 전단 1차원 IDCT2: 후단 1차원 IDCT1: front one-dimensional IDCT 2: rear one-dimensional IDCT
3: 중간 시프터4: 롬 LUT3: middle shifter 4: ROM LUT
도2는 종래 행렬 분해형 기반의 2차원 IDCT 구조 12 is a 2D IDCT structure based on a matrix decomposition method according to the related art.
도3은 종래 행렬 분해형 기반의 2차원 IDCT 구조 23 is a 2D IDCT structure 2 based on a conventional matrix decomposition type.
상기와 같은 목적을 달성하기 위하여 본 발명에 의한 2차원 IDCT는 압축된 영상 데이터를 입력 받아 첫 번째 1차원 IDCT를 처리하는 전단 1차원 IDCT(1)와 전단 1차원 IDCT로부터의 결과에 대한 두 번째 1차원 IDCT를 처리하는 후단 1차원 IDCT(2) 및 전단 1차원 IDCT로부터의 결과를 임시로 저장하고, 후단 1차원 IDCT에 비트 단위로 입력 제공하는 중간 시프터(3)로 구성된다.In order to achieve the above object, the 2D IDCT according to the present invention receives the compressed image data and processes the first 1D IDCT and processes the first 1D IDCT (1) and the second results from the front end 1D IDCT. It consists of an intermediate shifter 3 which temporarily stores the results from the preceding one-dimensional IDCT 2 and the preceding one-dimensional IDCT that processes the one-dimensional IDCT and inputs the bit-wise input to the subsequent one-dimensional IDCT.
2개의 1차원 IDCT는 모두 분할연산 알고리즘을 이용한다. 따라서 입력과 계수의 곱을 부분합을 저장하고 있는 롬과 이를 누적시키는 어큐물레이터(Accumulator)로대체한다.Both one-dimensional IDCTs use a partitioning algorithm. Therefore, we replace the product of the input and the coefficient with a ROM that stores a subtotal and an accumulator that accumulates it.
전단 1차원 IDCT는 8X8의 입력 데이터 행렬과 8개의 8X1의 IDCT 계수 중 선택된 하나의 벡터와의 행렬·벡터 곱을 수행하고, 이에 따른 결과로서 8X1의 1차원 IDCT 결과 벡터를 출력한다. 중간 시프터는 이러한 1차원 IDCT의 결과 벡터를 저장하고, 이 값을 후단 2차원 IDCT의 입력단에 비트 단위로 즉시 입력시킨다. 마지막으로, 후단 1차원 IDCT는 8X8의 IDCT 계수 행렬과 IDCT의 전단 1차원 IDCT의 결과인 8X1의 벡터와의 곱을 수행하므로서 최종적인 2차원 IDCT의 결과를 산출한다.The front-end one-dimensional IDCT performs a matrix-vector product of an 8X8 input data matrix and one selected vector of eight 8X1 IDCT coefficients, and outputs a one-dimensional IDCT result vector of 8X1 as a result. The intermediate shifter stores the result vector of this one-dimensional IDCT and immediately inputs this value into the input terminal of the rear two-dimensional IDCT bit by bit. Finally, the trailing one-dimensional IDCT calculates the final two-dimensional IDCT by performing the product of the 8X8 IDCT coefficient matrix and the 8X1 vector which is the result of the preceding one-dimensional IDCT of the IDCT.
도1에 나타내었듯이 전단 1차원 IDCT와 후단 1차원 IDCT 사이에는 전치과정이 없으므로, 전단 1차원 IDCT의 결과를 바로 후단 1차원 IDCT로 입력하여 사용할 수가 있다.As shown in FIG. 1, since there is no transposition between the front one-dimensional IDCT and the rear one-dimensional IDCT, the result of the front one-dimensional IDCT can be directly input and used as the rear one-dimensional IDCT.
이상에서 설명한 바와 같이, 본 발명은 행렬 분해형 2차원 IDCT에서 전치과정을 제거한 구조로써, 적은 면적과 적은 초기 지연 시간을 갖는다.As described above, the present invention is a structure that eliminates the transposition process in the matrix decomposition type two-dimensional IDCT, has a small area and a small initial delay time.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010051462A KR20030017251A (en) | 2001-08-24 | 2001-08-24 | Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010051462A KR20030017251A (en) | 2001-08-24 | 2001-08-24 | Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20030017251A true KR20030017251A (en) | 2003-03-03 |
Family
ID=27720815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010051462A KR20030017251A (en) | 2001-08-24 | 2001-08-24 | Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20030017251A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100898401B1 (en) * | 2007-01-25 | 2009-05-21 | 주식회사 씬멀티미디어 | Iq/idct apparatus of video decoder |
KR20190002304U (en) * | 2018-03-07 | 2019-09-18 | 주식회사 혜인샌더 | Protective Unit for Proteting Connections of Chamber for Electronic Devices Manufacturing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950016342A (en) * | 1993-11-04 | 1995-06-17 | 배순훈 | Two-dimensional inverse discrete cosine transform device |
KR950024573A (en) * | 1994-01-18 | 1995-08-21 | 배순훈 | Station discrete cosine converter |
KR19990060479A (en) * | 1997-12-31 | 1999-07-26 | 구자홍 | Inverse Discrete Cosine Device |
KR20000045668A (en) * | 1998-12-30 | 2000-07-25 | 구자홍 | Method for performing 2-dimensional inverse discrete cosine transform |
KR20020084334A (en) * | 2001-04-27 | 2002-11-07 | 김희석 | Architecture of 2D IDCT for reduction of the Memory size |
-
2001
- 2001-08-24 KR KR1020010051462A patent/KR20030017251A/en not_active Application Discontinuation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR950016342A (en) * | 1993-11-04 | 1995-06-17 | 배순훈 | Two-dimensional inverse discrete cosine transform device |
KR950024573A (en) * | 1994-01-18 | 1995-08-21 | 배순훈 | Station discrete cosine converter |
KR19990060479A (en) * | 1997-12-31 | 1999-07-26 | 구자홍 | Inverse Discrete Cosine Device |
KR20000045668A (en) * | 1998-12-30 | 2000-07-25 | 구자홍 | Method for performing 2-dimensional inverse discrete cosine transform |
KR20020084334A (en) * | 2001-04-27 | 2002-11-07 | 김희석 | Architecture of 2D IDCT for reduction of the Memory size |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100898401B1 (en) * | 2007-01-25 | 2009-05-21 | 주식회사 씬멀티미디어 | Iq/idct apparatus of video decoder |
KR20190002304U (en) * | 2018-03-07 | 2019-09-18 | 주식회사 혜인샌더 | Protective Unit for Proteting Connections of Chamber for Electronic Devices Manufacturing |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100965704B1 (en) | 2-d transforms for image and video coding | |
US7127482B2 (en) | Performance optimized approach for efficient downsampling operations | |
Fan | Fast 2-dimensional 4$ times $4 forward integer transform implementation for H. 264/AVC | |
Dhandapani et al. | Area and power efficient DCT architecture for image compression | |
JPH089389A (en) | Parallel decoder of digital video signal | |
KR100270799B1 (en) | Dct/idct processor | |
US7263544B2 (en) | Performance optimized approach for efficient numerical computations | |
KR100313217B1 (en) | Pipeline DCT device | |
AU2002259268A1 (en) | Apparatus and method for encoding and computing a discrete cosine transform using a butterfly processor | |
KR20030017251A (en) | Reduction of transposition process from the two dimensional inverse discrete cosine transform(2-D IDCT) based on the row-column decomposition | |
Fanucci et al. | Data driven VLSI computation for low power DCT-based video coding | |
Hung et al. | Statistical inverse discrete cosine transforms for image compression | |
US7756351B2 (en) | Low power, high performance transform coprocessor for video compression | |
EP1406179A1 (en) | Dct matrix decomposing method and dct device | |
CN110737869B (en) | DCT/IDCT multiplier circuit optimization method and application | |
US7136890B2 (en) | Inverse discrete cosine transform apparatus | |
KR100262645B1 (en) | Idct device | |
KR0178746B1 (en) | Half pixel processing unit of macroblock | |
KR100433709B1 (en) | Discrete cosine transform method of distributed arithmetic | |
Jessintha et al. | Energy efficient, architectural reconfiguring DCT implementation of JPEG images using vector scaling | |
Chuang et al. | Direct splitting and merging of 2-D DCT in the DCT domain | |
JP3135894U (en) | Data converter | |
Lin et al. | Nearly lossless content-dependent low-power DCT design for mobile video applications | |
US6993550B2 (en) | Fixed point multiplying apparatus and method using encoded multiplicand | |
Chien et al. | A recursive DCT algorithm with new distributed arithmetic |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |