KR950024423A - Monostable Multivibrator - Google Patents

Monostable Multivibrator Download PDF

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Publication number
KR950024423A
KR950024423A KR1019940001468A KR19940001468A KR950024423A KR 950024423 A KR950024423 A KR 950024423A KR 1019940001468 A KR1019940001468 A KR 1019940001468A KR 19940001468 A KR19940001468 A KR 19940001468A KR 950024423 A KR950024423 A KR 950024423A
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KR
South Korea
Prior art keywords
output
flip
flop
pulse width
pulse
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KR1019940001468A
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Korean (ko)
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KR960005979B1 (en
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진성곤
팽교선
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김광호
삼성전자 주식회사
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Priority to KR1019940001468A priority Critical patent/KR960005979B1/en
Publication of KR950024423A publication Critical patent/KR950024423A/en
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Publication of KR960005979B1 publication Critical patent/KR960005979B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/033—Monostable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

RC시정수에 의하지 않고 펄스폭을 결정하는 단안정 멀티바이브레타가 개시된다.A monostable multivibrator is disclosed which determines the pulse width regardless of the RC time constant.

본 발명에 따른 단안정 멀티바이브레타는 단안정 펄스신호의 펄스폭에 대응하는 계수치를 결정하는 래치; 트리거펄스에 의해 구동되는 D플립플롭;Monostable multivibrator according to the present invention comprises a latch for determining a coefficient value corresponding to the pulse width of the monostable pulse signal; A D flip-flop driven by a trigger pulse;

트리거펄스에 의해 구동되고 D플립플롭의 출력을 래치에 의해 설정된 계수치에 상응하는 클럭주기만큼 지연시켜 출력하는 가변쉬프트 레지스터; 그리고 D플립플롭의 출력이 발생되는 시점부터 가변쉬프트 레지스터의 출력이 발생하는 시점까지의 주기를 갖는 펄스신호를 발생하는 노아게이트를 포함한다.A variable shift register driven by a trigger pulse and delaying an output of the D flip-flop by a clock period corresponding to a count value set by the latch; And a no-gate for generating a pulse signal having a period from the time when the output of the D flip-flop is generated to the time when the output of the variable shift register is generated.

본 발명은 래치를 통하여 설정된 클럭주기만큼의 펄스폭을 갖는 단안정 펄스신호를 제공함으로써, 안정된 동작을 보이는 단안정 멀티바이브레타를 제공하는 효과를 갖는다.The present invention has the effect of providing a monostable multivibrator exhibiting stable operation by providing a monostable pulse signal having a pulse width equal to a set clock period through a latch.

Description

단안정 멀티바이브레타Monostable Multivibrator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 단안정 멀티바이브레타의 일 실시예를 보이는 회로도이다.3 is a circuit diagram showing an embodiment of a monostable multivibrator according to the present invention.

Claims (6)

단안정 펄스신호의 펄스폭에 대응하는 계수치를 결정하는 펄스폭 설정수단; 트리거펄스에 의해 구동되는 플립플롭; 상기 트리거펄스에 의해 구동되고 상기 플립플롭의 출력을 상기 펄스폭 설정수단에 의해 설정된 계수치에 상응하는 클럭주기만큼 지연시켜 출력하는 지연수단; 상기 플립플롭의 출력이 발생되는 시점부터 상기 지연수단의 출력이 발생하는 시점까지의 주기를 갖는 펄스신호를 발생하는 게이트수단을 포함하는 단안정 멀티바이브레타.Pulse width setting means for determining a coefficient value corresponding to the pulse width of the monostable pulse signal; A flip-flop driven by a trigger pulse; Delay means which is driven by the trigger pulse and delays the output of the flip-flop by a clock period corresponding to the count value set by the pulse width setting means; And gate means for generating a pulse signal having a period from the time when the output of the flip-flop is generated to the time when the output of the delay means is generated. 제1항에 있어서, 상기 게이트수단의 출력에 의해 상기 플립플롭을 리세트시키는 제2게이트수단을 더 구비함을 특징으로 하는 단안정 멀티바이브레타.The monostable multivibrator according to claim 1, further comprising a second gate means for resetting the flip-flop by an output of the gate means. 제1항에 있어서, 상기 펄스폭 설정수단은 마이크로프로세서에 의해 제어되며 상기 마이크로프로세서에서 제공되는 데이터를 래치하여 상기 지연수단에 제공하는 래치임을 특징으로 하는 단안정 멀티바이브레타.The monostable multivibrator according to claim 1, wherein the pulse width setting means is a latch controlled by a microprocessor and latches data provided from the microprocessor to provide the delay means. 제1항에 있어서, 상기 펄스폭 설정수단은 아날로그값의 계수치를 설정하는 수단; 상기 설정수단에 의해 설정된 아날로그 계수치를 디지탈 계수치로 변환하는 A/D변환기; 상기 A/D변환기에 의해 변환된 디지탈 계수치를 래치하여 상기 지연수단에 제공하는 래치를 구비함을 특징으로 하는 단안정 멀티바이브레타.2. The apparatus of claim 1, wherein the pulse width setting means comprises: means for setting a count value of an analog value; An A / D converter for converting an analog coefficient value set by said setting means into a digital coefficient value; And a latch for latching the digital coefficient value converted by the A / D converter and providing the delay coefficient to the delay means. 제1항에 있어서, 상기 지연수단은 상기 펄스폭 설정수단애 의해 설정된 계수값을 프리세트값으로 로드하고, 그에 인가되는 클럭신호에 의해 상기 플립플롭의 출력을 쉬프트시켜 출력시키는 가변 쉬프트 레지스터임을 특징으로 하는 단안정 멀티바이브레타.2. The variable shift register according to claim 1, wherein said delay means is a variable shift register which loads a count value set by said pulse width setting means as a preset value and shifts and outputs the output of said flip-flop by a clock signal applied thereto. Monostable multivibrator. 제1항에 있어서, 상기 지연수단은 상기 플립플롭의 출력에 의해 인에이블되어 그에 인가되는 클럭신호를 계수하는 카운터; 상기 카운터의 출력과 상기 펄스폭 설정수단의 출력이 같으면 상기 게이트수단에 출력을 제공하는 제3게이트수단을 구비함을 특징으로 하는 단안정 멀티바이브레타.2. The apparatus of claim 1, wherein the delay means comprises: a counter that is enabled by an output of the flip-flop and counts a clock signal applied thereto; And a third gate means for providing an output to the gate means if the output of the counter and the output of the pulse width setting means are the same. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940001468A 1994-01-27 1994-01-27 Mono stable multivibrater KR960005979B1 (en)

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Application Number Priority Date Filing Date Title
KR1019940001468A KR960005979B1 (en) 1994-01-27 1994-01-27 Mono stable multivibrater

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Application Number Priority Date Filing Date Title
KR1019940001468A KR960005979B1 (en) 1994-01-27 1994-01-27 Mono stable multivibrater

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KR950024423A true KR950024423A (en) 1995-08-21
KR960005979B1 KR960005979B1 (en) 1996-05-06

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