KR950024306A - Method of forming a connection between multilayer wirings in a semiconductor device - Google Patents

Method of forming a connection between multilayer wirings in a semiconductor device Download PDF

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Publication number
KR950024306A
KR950024306A KR1019940000605A KR19940000605A KR950024306A KR 950024306 A KR950024306 A KR 950024306A KR 1019940000605 A KR1019940000605 A KR 1019940000605A KR 19940000605 A KR19940000605 A KR 19940000605A KR 950024306 A KR950024306 A KR 950024306A
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KR
South Korea
Prior art keywords
forming
ion implantation
insulating film
interlayer insulating
plug
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KR1019940000605A
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Korean (ko)
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KR970003732B1 (en
Inventor
김환명
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문정환
금성일렉트론 주식회사
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Priority to KR94000605A priority Critical patent/KR970003732B1/en
Publication of KR950024306A publication Critical patent/KR950024306A/en
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Publication of KR970003732B1 publication Critical patent/KR970003732B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 다층배선을 연결하는 목적으로 플러그를 형성하는 금속으로 텅스텐 대신에 루드늄을 사용하여 플러그를 형성할 부위의 층간절연막에 루드늄이온을 주입하여 산소 개스 분위기에서 열처리하여 루드늄이온이 주입된 부위의 층간절연막을 RuO2로 변화시켜 도전층화한다.The present invention is a metal for forming a plug for the purpose of connecting a multi-layer wiring by injecting ruthenium ions into the interlayer insulating film of the site where the plug is to be formed using rudium instead of tungsten and heat-treated in an oxygen gas atmosphere to inject the ruthenium ion The interlayer insulating film of the portion is changed to RuO 2 to form a conductive layer.

금속배선간의 연결부 형성 방법은, (가), 반도체 기판 위에 하층 금속 배선을 형성하고, 상기 금속배선 위에 층간절연막을 증착하고, 상기 층간 절연막위에 콘텍부위를 정의하는 포토레지스트 패턴을 형성하는 단계; (나), 상기 포토레지스트 패턴을 마스크로하여 콘택부위에 이온을 주입하여 층간절연막에 이온주입영역을 형성하는 단계; (다), 상기 이온주입영역을 열처리하여 도전성 플러그를 형성하는 단계; (라), 상기 플러그가 형성 된 층간절연막 상에 상층 금속배선을 형성하는 단계를 포함하여 이루어진다.Method for forming a connection between the metal wiring, (A) forming a lower metal wiring on the semiconductor substrate, depositing an interlayer insulating film on the metal wiring, and forming a photoresist pattern defining a contact portion on the interlayer insulating film; (B) forming an ion implantation region in the interlayer insulating film by implanting ions into the contact region using the photoresist pattern as a mask; (C) heat treating the ion implantation region to form a conductive plug; (D) forming an upper metal wiring on the interlayer insulating film having the plug formed thereon.

Description

반도체 장치의 다층 배선간 연결부 형성방법Method of forming a connection between multilayer wirings in a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 반도체 장치의 다층 배선간 연결부 형성방법을 도시한 것이다.2 illustrates a method for forming a connection portion between multilayer wirings in a semiconductor device according to the present invention.

Claims (8)

반도체 장치 금속배선간의 연결부 형성 방법에 있어서, (가), 반도체 기판 위에 하층 금속배선을 형성하고, 상기 금속배선 위에 층간절연막을 증착하고, 상기 층간절연막위에 콘택부위를 정의하는 포토레지스트 패턴을 형성하는 단계; (나), 상기 포토 패지스트 패턴을 마스크로하여 콘택부위에 이온을 주입하여 층간절연막에 이온주입영역을 형성하는 단계; (다), 상기 이온주입영역을 열처리하여 도전성 플러그를 형성하는 단계; (라), 상기 플러그가 형성된 층간절연막 상에 상층 금속배선을 형성하는 단계를 포함하는단계를 이루어지는 반도체 장치의 다층 배선관 연결부 형성방법.A method of forming a connection portion between semiconductor device metal wirings, comprising: (a) forming a lower metal wiring on a semiconductor substrate, depositing an interlayer insulating film on the metal wiring, and forming a photoresist pattern defining a contact portion on the interlayer insulating film; step; (B) forming an ion implantation region in the interlayer insulating film by implanting ions into a contact portion using the photo resist pattern as a mask; (C) heat treating the ion implantation region to form a conductive plug; And (d) forming an upper metal wiring on the interlayer insulating film having the plug formed thereon. 제1항에 있어서, 상기의 플러그 형성을 위하여 주입하는 이온은 Si보다 산소 원자에 더한 생성열이 작은 전이금속 중에서 선택되는 것을 특징으로 하는 반도체 장치의 다층 배선간 연결부 형성방법.The method of claim 1, wherein the ions implanted to form the plug are selected from transition metals having a smaller amount of heat generated in addition to oxygen atoms than Si. 제2항에 있어서, 상기 선택된 전이금속은 Ru인 것을 특징으로하는 반도체 장치의 다층 배선간 연결부 형성방법.The method of claim 2, wherein the selected transition metal is Ru. 제3항에 있어서, 상기의 이온주입에서 Ru이온은 Ru2+, Ru4+등으로 이온주입되는 이온주입원을 변화시키며 이온을 주입하는 것을 특징으로 하는 반도체 장치의 다층 배선간 연결부 형성방법.4. The method of claim 3, wherein in the ion implantation, the Ru ions are implanted with the ion implanted by changing the ion implantation source into Ru 2+ , Ru 4+, or the like. 제1항에 있어서, 상기의 이온주입은 플러그의 길이에 상응하여 이온이 주입되도록 이온주입에너지를 변화시키며 주입하는 것을 특징으로 하는 반도체 장치의 다층 배선간 연결부 형성방법.The method of claim 1, wherein the ion implantation is performed by varying ion implantation energy so that ions are implanted in correspondence with a length of a plug. 제2항에 있어서, 상기의 이온주입은 플러그의 길이에 상응하여 이온이 주입되도록 이온 주입 에너지를 변화시키며 주입하는 것을 특징으로하는 반도체 장치의 다층 배선간 연결부 형성방법.The method of claim 2, wherein the ion implantation is performed by varying ion implantation energy so that ions are implanted in correspondence with the length of the plug. 제3항에 있어서, 상기의 이온주입은 플러그의 길이에 상응하여 이온이 주입도도록 이온 주입 에너지를 변화시키며 주입하는 것을 특징으로하는 반도체 장치의 다층 배선간 연결부 형성방법.The method of claim 3, wherein the ion implantation is performed by varying ion implantation energy so that ions are implanted corresponding to the length of the plug. 제1항에 있어서, 상기의 열처리 공정은 산소 개스 분위기하에서 400℃ 내지 800℃ 의 온도 범위에서 실시하는 것을 특징으로하는 반도체 장치의 다층 배선간 형성방법.The method of claim 1, wherein the heat treatment step is performed at an oxygen gas atmosphere at a temperature in the range of 400 ° C to 800 ° C. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR94000605A 1994-01-14 1994-01-14 Method of forming the multilayer wiring on the semiconductor device KR970003732B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR94000605A KR970003732B1 (en) 1994-01-14 1994-01-14 Method of forming the multilayer wiring on the semiconductor device

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Application Number Priority Date Filing Date Title
KR94000605A KR970003732B1 (en) 1994-01-14 1994-01-14 Method of forming the multilayer wiring on the semiconductor device

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KR950024306A true KR950024306A (en) 1995-08-21
KR970003732B1 KR970003732B1 (en) 1997-03-21

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