KR950022603A - Link Handling System of Electronic Switching System (LPMB-E) - Google Patents

Abstract

The present invention relates to a link processing system of an electronic switch, and more particularly, to a link processing system of an electronic switch that can increase the operation and maintenance, cost efficiency, etc. by reducing the hardware and improving the function of the system. The LPMB-E of the all-electronic switch provided by the present invention includes an alarm driver, an NMI generator, a PIO circuit, an input / output decoder, an alarm interbase, an SIO circuit, a DMA circuit, a clock generator, a main processor, It consists of buffer and MMC interbase, CTC, ERU circuit, memory shank circuit, main memory, memory selection circuit, multiplexer, memory control circuit, RAM, parity check and circuit. It is invented as a single circuit pack by changing and simplifying the hardware, changing the chip, etc., so that the exchanger system can be simplified while offering functions similar to those of the standard. In the end of life, the range of substitution is wide. In addition, by switching to the simplification of the circuit pack, the power supply circuit pack can also be replaced with a low-cost circuit pack, resulting in a price-to-volume advantage.

Description

Link Handling System of Electronic Switching System (LPMB-E)

Since this is an open matter, no full text was included.

3 is a detailed block diagram of an LPMB-E according to an embodiment of the present invention.

Claims (1)

System faults or alarms generated at each level of the exchange, including: an alarm driver for requesting or reporting an action at a higher level; a non-maskable interrupt generator (MNI) generating a priority interrupt; the alarm driver and the MNI generator A parallel input / output circuit connected to the control unit to control parallel input / output of data, an alarm interface for transmitting an alarm between the host system and the RSS system, a serial input / output circuit connected to the alarm interface to control serial input / output of the data, A main processor for controlling the entire system, a direct memory access circuit connected to the serial input / output circuit so that a memory directly inputs / outputs without passing through a central processing unit, a clock is generated to generate the main processor, the serial input / output circuit, and the Diagram of direct access circuit A clock generator for transmitting a signal, a man machine interbase for controlling communication by a user's operation, and a counter timer circuit for exchanging data with the man machine interface interface and operating as a counter or a timer according to an output signal of the man machine interface. And a control buffer for controlling the output of the main processor, an input / output decoder for receiving an output of the parallel input / output circuit and coding an input / output signal, and controlled by the man machine interface and the town timer timer circuit. An ERU circuit that generates and stores a code in a format and compares the stored code with the regenerated code at the time of reading and recovers normal data in the event of a bit error, and is inputted from the ERU circuit. A first buffer for transmitting data to the input / output decoder; A main memory for storing various data of an all-electronic exchange, a memory check circuit for receiving the output of the parallel input / output circuit, and a second buffer for transmitting the output of the main memory to the memory check circuit; A multiplexer that receives an output from an ERU circuit and generates one output; a memory selector circuit that receives the output of the multiplexer and selects the main memory; A link processing system of an electronic switching system comprising a memory control circuit for controlling and a parity circuit for error detection of data that may occur during bus communication and memory read / write. ※ Note: The disclosure is based on the initial application.