KR950020284A

KR950020284A - Up / down scroll circuit

Info

Publication number: KR950020284A
Application number: KR1019930030566A
Authority: KR
Inventors: 신광철; 김대현
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1993-12-29
Filing date: 1993-12-29
Publication date: 1995-07-24

Abstract

본 발명은 모니터상에서 디스플레이 된 화면 데이타를 라인단위로 상/하 이동시키는 회로에 관한 것이다. 종래의 화면이동 방법은 중앙처리장치 내부에서 어셈블리언어의 명령어들을 사용하여 비디오램의 화면 데이타를 직접 제어함으로서 화면이동을 하도록 한 것이나, 본 발명은 중앙처리장치의 외부에 선입력 선출력 제어기와 그래픽장치와, 메모리제어기와, 멀티플렉서와, 비디오램을 사용하여 회로적으로 설계하여 중앙처리장치에서 'OUT'명령만을 사용하여 화면 데이타를 라인단위로 상/하로 이동시킬 수 있도록 한 것을 특징으로 한다. 본 발명은 중앙처리장치의 'OUT'명령어만을 사용하여 화면이동을 실현할 수 있다는 잇점이 있으며, 화면이동회로를 아식(ASIC)칩으로 구현시 어드레스 핀을 14핀이상 줄일 수 있으므로 패키지의 단순화로 인해 설계가 용이하여 경제적으로 사용할 수 있다.The present invention relates to a circuit for moving screen data displayed on a monitor up / down line by line. Conventional screen shift method is to move the screen by directly controlling the screen data of the video RAM using the instructions of the assembly language in the central processing unit, the present invention is a pre-input line output controller and graphics on the outside of the central processing unit It is designed by using a device, a memory controller, a multiplexer, and a video RAM to design a circuit so that the screen data can be moved up and down line by line using only the 'OUT' command in the central processing unit. The present invention has the advantage that the screen movement can be realized by using only the 'OUT' instruction of the central processing unit, and the address pin can be reduced by more than 14 pins when the screen shift circuit is implemented as an ASIC chip. Easy to design and economical to use.

Description

Up / down scrolling circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 상/하 화면이동회로의 블럭도.1 is a block diagram of an up / down screen movement circuit.

제2도는 상/하 화면이동기능 실현을 위한 타이밍도이다.2 is a timing diagram for realizing the up / down screen movement function.

Claims

A pre-input line that temporarily stores the contents of the data registers 6 and each of the address registers 7 and 8 transferred from the central processing unit (CPU) through the data bus and performs the pre-input pre-output memory (FIFO) An output memory (FIFO) controller 1; When the SCROLL-MODE signal is operated as HIGH, the SCROLL-FLAG signal is operated and the data of the video RAM 5 and the data output from the pre-input / output controller 1 are displayed. A graphics device 2 for combining; The CPU receives the write signal (WR ^* ) signal generated by the 'OUT' command and the signal (D-CONTAIN) which means that it has data from the pre-input pre-output memory (FIFO) controller (1). A memory controller 3 for generating each signal for controlling the RAM 5, a SCROLL signal, and a 2-bit plane address signal; The scrolling address using the SCROLL-FLAG signal, which is the output signal of the graphics device 2, and the SCROLL signal of the memory controller 3, as a control input. Select one signal from among the scroll address (SCROLL ADDR.) Signal output from the register (9) and the vertical address (VER. ADDR.) Signal output from the pre-input line output memory (FIFO) controller (1). A multiplexer (4) for inputting the vertical address (VER. ADDR.) Of the video RAM (5); The 7-bit horizontal address (HORI, ADDR.) In the pre-input line output memory (FIFO) controller (1) and the 2 bits of the plane address (PLANE ADDR.) Signal, which is the output signal of the memory controller (3), are the lower counter bits. By combining the horizontal address (HORI.ADDR.) And the signal output from the multiplexer 4 with the 9-bit address as the vertical address (VER.ADDR.), The respective control inputs (RAS) output from the memory controller (3). ^* , CAS ^* , CE ^* , WE ^* ) Up / Down screen shifting circuit characterized by consisting of video RAM (5) which transmits data to graphic device (2) and saves data back to memory after graphic operation. .

※ Note: The disclosure is based on the initial application.