KR950020132A

KR950020132A - I / O processor memory partitioning method

Info

Publication number: KR950020132A
Application number: KR1019930031635A
Authority: KR
Inventors: 최재훈
Original assignee: 이헌조; 엘지전자 주식회사
Priority date: 1993-12-30
Filing date: 1993-12-30
Publication date: 1995-07-24
Also published as: KR960005107B1

Abstract

본 발명은 타이컴 시스템의 입출력 처리기 메모리를 효과적으로 분할 사용하는 방법에 관한 것이다. 종래의 입출력 처리기 메모리 분할 방법은 고정적으로 메모리를 7MB와 1MB로 나누어 사용하기 때문에 사용되는 통신망의 보드가 없으면 1MB의 메모리를 낭비하게 되며 사용하는 통신망의 보드가 많으면 1MB의 메모리로는 부족하기 때문에 시스템에 사용하는 통신망의 보드를 1MB가 허용하는 범위까지로 제한해야 하는 문제점이 있었다. 따라서, 본 발명에 의한 입출력 처리기 메모리 분할 방법은 블럭 입출력 장치용 메모리의 영역과 문자 일출력 장치용 메모리의 영역을 초기화하는 제1단계와 시스템에서 사용되는 근거리 통신망 보드가 사용하는 메모리의 크기를 검출하는 제2단계와, 시스템에서 사용되는 원거리 통신망 보드가 사용하는 메모리의 크기를 검출하는 제3단계와, 상기 블럭 입출력 장치용 메모리의 영역과 상기 문자 입출력 장치용 메모리의 영역을 통신망 보드에서 사용하는 메모리의 크기에 따라 새롭게 분리하는 제4단계를 포함하여 통신망 보드의 갯수에 관계없이 가장 효율적으로 메모리를 운용할 수 있는 효과가 있다.The present invention relates to a method of effectively partitioning and using an input / output processor memory of a tycom system. In conventional input / output processor memory partitioning method, the memory is fixedly divided into 7MB and 1MB, so if there is no board of the communication network used, 1MB of memory is wasted, and if there are many boards of the communication network, 1MB of memory is insufficient. There was a problem in that the board of the network used in the system should be limited to the range allowed by 1MB. Accordingly, the input / output processor memory partitioning method according to the present invention detects the size of the memory used by the local area network board used in the system and the first step of initializing the area of the memory for the block I / O device and the area of the memory for the character output device. And a third step of detecting the size of the memory used by the telecommunication network board used in the system; and using the area of the memory for the block I / O device and the area of the memory for the character I / O device in the network board. Including the fourth step of newly separating according to the size of the memory, the memory can be operated most efficiently regardless of the number of network boards.

Description

I / O Processor Memory Partitioning Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래 입출력 처리기 메모리 분할도.1 is a conventional input / output processor memory partition diagram.

제 2 도는 본 발명에 의한 입출력 처리기 메모리 분할 방법의 순서도이다.2 is a flowchart of the input / output processor memory partitioning method according to the present invention.

Claims

A first step of separating and initializing the input / output processor memory into an area of a block input / output device memory and an area of a character input / output device memory; a second step of detecting a size of a memory used by a local area network board used in the system; A third step of detecting the size of the memory used by the telecommunication network board used in the system; and securing the area of the memory for the character input / output device by the size of the memory used by the short distance and the telecommunication network board, and the remaining I / O processor memory area. And a fourth step of using the same as an area of a memory for a block I / O device.

2. The method of claim 1, wherein the first step is to initialize the area of the memory for the block I / O device to 8 MB and the area of the memory for the character I / O device to 0 MB.

3. The method of claim 2, wherein the fourth step subtracts the area of the character I / O memory output in the third step from the area of the block I / O memory and outputs a new area of the memory for the block I / O device. I / O processor memory partitioning method.

The method of claim 1, wherein the second step detects the number of local area network boards used, adds the number of boards multiplied by the size of memory used per board, and adds the new character input / output to the area of the memory for the original character input / output device. An input / output processor memory partitioning method characterized by outputting to an area of a device memory.

The method of claim 1, wherein the third step detects the number of telecommunication network boards used, adds the number of boards multiplied by the size of the memory used per board, and adds the new character I / O to the area of the memory for the original character I / O device. An input / output processor memory partitioning method characterized by outputting to an area of a device memory.

※ Note: The disclosure is based on the initial application.