KR950016017A - Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System - Google Patents

Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System Download PDF

Info

Publication number
KR950016017A
KR950016017A KR1019930025981A KR930025981A KR950016017A KR 950016017 A KR950016017 A KR 950016017A KR 1019930025981 A KR1019930025981 A KR 1019930025981A KR 930025981 A KR930025981 A KR 930025981A KR 950016017 A KR950016017 A KR 950016017A
Authority
KR
South Korea
Prior art keywords
phase synchronization
received signal
offset voltage
communication system
digital communication
Prior art date
Application number
KR1019930025981A
Other languages
Korean (ko)
Inventor
박재선
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019930025981A priority Critical patent/KR950016017A/en
Publication of KR950016017A publication Critical patent/KR950016017A/en

Links

Abstract

전압제어발진기(5)및 분주기(6)를 통해 혼합기(7)에 가해지는 신호로 부터 수신정도[d(t)]를 얻게 되나 두신호의 위상이 정확히 일치하지 않으면 수신정보[d(t)]에 잡음이 섞이게 된다. 그러므로 이러한 위상오차를 최대한 줄여 시스템내의 잡음을 최소화 시켜야 하는데 주위온도 변화에 따른 전압제어발진기의 출력 주파수가 바뀌게 되기 때문에 수신신호와 동기신호간에 위상오차가 발생되는 것을 방지하기 위해 오프셋 전압을 발생토록 감온소자인 더미스터를 사용하여 이러한 위상 오차를 줄여줄 수 있다.The reception accuracy [d (t)] is obtained from the signal applied to the mixer 7 through the voltage controlled oscillator 5 and the divider 6, but the reception information [d (t) )] Is mixed with noise. Therefore, it is necessary to minimize the noise in the system by minimizing the phase error. Since the output frequency of the voltage controlled oscillator is changed according to the change of ambient temperature, the temperature is reduced to generate offset voltage to prevent phase error between the received signal and the synchronization signal. The device's dummyster can be used to reduce this phase error.

Description

디지탈 통신시스템에서 수신신호의 위상동기 에러 보상방법 및 회로Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 제1도의 전압제어 발진시(VCO)(5)의 제어 전압(VT)에 의한 출력 주파수 특성도.2 is an output frequency characteristic diagram according to the control voltage V T of the voltage controlled oscillation (VCO) 5 of FIG.

제3도는 제1도의 전압제어발진기(VCO)(5)의 주파수 특성도.3 is a frequency characteristic diagram of the voltage controlled oscillator (VCO) 5 of FIG.

제4도는 본 발명에 따른 회로도.4 is a circuit diagram according to the present invention.

Claims (5)

자승회로(1), 위상검출기(2), 저역통과 필터(4, 8), VCO(5), 분주기(6),혼합기(7)를 구비한 디지탈 송신 수신시스템의 수신신호의 보정방법에 있어서, 상기 수신시스템의 주변 온도변화에 따른 위상동기에러를 보정하기위한 오프셋전압을 발생하고, 상기 위상검출기(2)의 출력과 상기 오프셋 전압을 가산하여 상기 저역통과 필터(4)에 제공하여 위상동기에러를 보정함을 특징으로 하는 디지탈 통신시스템에서 수신신호의 위상동기에러 보상방법.A method for correcting a received signal of a digital transmission receiving system having a square circuit (1), a phase detector (2), low pass filters (4, 8), a VCO (5), a divider (6), and a mixer (7). An offset voltage is generated to correct phase synchronization according to a change in ambient temperature of the receiving system, and the output of the phase detector 2 and the offset voltage are added to the low pass filter 4 to provide a phase. A method for compensating for phase synchronization of a received signal in a digital communication system, characterized in that the synchronization error is corrected. 자승회로(1), 위상검출기(2), 저역통과 필터(4, 8), VCO(5), 분주기(6), 혼합기(7)를 구비한 디지탈 송신 수신시스템의 수신신호의 보정회로에 있어서, 상기 수신시스템의 주변 온도변화에 따른 위상동기에러를 보정하기위한 오프셋전압을 발생하는 오프셋 전압 발생부(400)와, 상기 저역통과 필터(4)의 출력과 오프셋전압 발생부(400)의 출력을 가산하여 전압제어 발진기(5)로 제공토록 구성함을 특징으로 하는 디지탈 통신시스템에서 수신신호의 위상동기에러 보상방법.To a correction signal correction circuit of a digital transmission receiving system having a square circuit (1), a phase detector (2), low pass filters (4, 8), a VCO (5), a divider (6), and a mixer (7). The offset voltage generator 400 is configured to generate an offset voltage for correcting phase synchronization according to a change in the ambient temperature of the receiving system, and the output of the low pass filter 4 and the offset voltage generator 400. A method for compensating for phase synchronization of a received signal in a digital communication system, characterized in that the output is added and provided to the voltage controlled oscillator (5). 제2항에 있어서, 오프셋 전압발생부(400)가 저항(10)과 온도감지기를 병렬로 연결하는 상기 저항(10)과 온도감지기의 구성으로 부터 저항(11)을 직렬로 구성됨을 특징으로 하는 디지탈 통신시스템에서 수신신호의 위상동기에러 보상방법.The method of claim 2, characterized in that the offset voltage generator 400 is configured in series with the resistor 11 from the configuration of the resistor 10 and the temperature sensor connecting the resistor 10 and the temperature sensor in parallel. A method for compensating phase synchronization of a received signal in a digital communication system. 제3항에 있어서, 온도감지기가 더미스터임을 특징으로 하는 디지탈 통신시스템에서 수신신호의 위상동기에러 보상회로.4. The phase synchronization compensation circuit according to claim 3, wherein the temperature sensor is a dummyster. 제2항에 있어서, 오프셋 전압발생부(400)가 위상동기루프 특성에 맞게 1개 이상의 온도감지기와 1개이상의 저항 및 액티브 소자를 포함하는 것을 특징으로 하는 디지탈 통신시스템에서 수신신호의 위상동기에러 보상회로.3. The phase synchronization of a received signal in a digital communication system according to claim 2, wherein the offset voltage generator 400 includes at least one temperature sensor, at least one resistor and an active element in accordance with the phase synchronization loop characteristics. Compensation circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930025981A 1993-11-30 1993-11-30 Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System KR950016017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930025981A KR950016017A (en) 1993-11-30 1993-11-30 Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930025981A KR950016017A (en) 1993-11-30 1993-11-30 Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System

Publications (1)

Publication Number Publication Date
KR950016017A true KR950016017A (en) 1995-06-17

Family

ID=66826535

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930025981A KR950016017A (en) 1993-11-30 1993-11-30 Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System

Country Status (1)

Country Link
KR (1) KR950016017A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433634B1 (en) * 2002-04-19 2004-05-31 한국전자통신연구원 Adaptive loop gain control circuit for voltage controlled oscillator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100433634B1 (en) * 2002-04-19 2004-05-31 한국전자통신연구원 Adaptive loop gain control circuit for voltage controlled oscillator

Similar Documents

Publication Publication Date Title
US4755774A (en) Two-port synthesizer modulation system employing an improved reference phase modulator
EP0563945A1 (en) Phase locked loop
KR101035827B1 (en) Voltage-controlled oscillator presetting circuit
US6342798B1 (en) PLL circuit used temperature compensated VCO
US5343169A (en) Frequency locked loop
AU7588494A (en) Digital clock generator
FI85433B (en) KRETSARRANGEMANG FOER KOMPENSERING AV TEMPERATURDRIFTEN I EN FASDETEKTOR.
US5719827A (en) Highly stable frequency generator
EP0209754A2 (en) Two-part synthesizer modulation system using a reference phase modulator
KR950016017A (en) Phase Synchronization Error Compensation Method and Circuit of Received Signal in Digital Communication System
US4816782A (en) Modulation sensitivity correction circuit for voltage-controlled oscillator
US5900751A (en) Automatic frequency control circuit with simplified circuit constitution
US4688003A (en) Feed-forward error correction for sandaps and other phase-locked loops
US5493257A (en) Modulator with biasing circuit to minimize output distortion
US5654674A (en) Oscillator control circuit with phase detection feedback
US5821819A (en) Base station oscillator tuned with received clock signal
JPH0377434A (en) Local oscillation circuit
US5751196A (en) Circuit arrangement for compensating frequency deviations of a voltage-controlled oscillator, using a second oscillator
KR970055566A (en) Phase Synchronization Loop for Improving Phase Synchronization Time
JPH06252642A (en) Control circuit for frequency characteristic of digitally controlled temperature compensation type crystal oscillator
US4612511A (en) FM demodulator including PLL and improved circuitry for eliminating distortion in the output thereof
US6459342B1 (en) System and method for controlling an oscillator
KR100195280B1 (en) Phase conversion apparatus regardless of element varidation
KR960000055Y1 (en) Pll control circuit
SU582574A1 (en) Phase-wise frequency tuning device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination