KR950016013A - How to write error correction code - Google Patents

How to write error correction code Download PDF

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Publication number
KR950016013A
KR950016013A KR1019930024143A KR930024143A KR950016013A KR 950016013 A KR950016013 A KR 950016013A KR 1019930024143 A KR1019930024143 A KR 1019930024143A KR 930024143 A KR930024143 A KR 930024143A KR 950016013 A KR950016013 A KR 950016013A
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KR
South Korea
Prior art keywords
code
error correction
bit
codewords
correction code
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KR1019930024143A
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Korean (ko)
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KR950010769B1 (en
Inventor
이상철
류승문
김도선
사공창대
안승준
이성민
이광억
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황해웅
국방과학연구소
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Priority to KR1019930024143A priority Critical patent/KR950010769B1/en
Publication of KR950016013A publication Critical patent/KR950016013A/en
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Publication of KR950010769B1 publication Critical patent/KR950010769B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

본 발명은 전송정보의 2비트 에러를 검출하고, 1비트 에러를 정정할 수 있게 한 에러정정코드 작성방법에 관한 것으로, 전송정보의 2비트 에러검출 및 1비트 에러정정을 위해서는 각 코드워드간 해밍거리가 4인 완전 코드세트가 필요하게 된다. 이러한 점을 감안하여, 7비트의 최장부호열을 1비트씩 시프트하여 7개의 부호열을 만들고, 그 부호열 처음에 "0"비트를 각기 추가하여 코드길이가 8인 7개의 부호열을 만들며, 그 7개의 부호열에 "000000000"의 코드워드를 추가하여 8개의 코드워드를 만들고 그 8개 코드워드 각각의 정반대(Antipodal)값을 코드워드로 만들어 총 16개의 코드워드를 만들며, 상기 16개의 코드워드에 "AAH"값을 모듈-2 가산시켜 에러정정코드를 만듦으로써, 각 코드워드간 해밍거리가 4인 완전 에러정정코드가 되게 한 것이다.The present invention relates to a method for generating an error correction code that detects a 2-bit error of transmission information and corrects a 1-bit error. Hamming between codewords is used for 2-bit error detection and 1-bit error correction of transmission information. You need a complete code set with a distance of 4. With this in mind, seven code strings are created by shifting the 7-bit longest code string by one bit, and adding seven "0" bits at the beginning of the code string to make seven code strings having a code length of eight. Eight codewords are added by adding "000000000" codewords to the seven code strings and 16 codewords are made by making antipodal values of each of the eight codewords into codewords. By adding "AAH" to Module-2 and generating an error correction code, the code is a complete error correction code with a Hamming distance of 4 between each codeword.

Description

에러정정코드 작성방법How to write error correction code

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2(a) 도 내지 제 2(c) 도는 본 발명에 의한 부호열 세트 작성과정 설명도.2 (a) to 2 (c) are explanatory diagrams of a code string set creation process according to the present invention.

제 3 도는 제 2(c) 도의 부호열 세트에 AAH를 모듈-2 가산하여 만든 본 발명의 에러정정코드 테이블.3 is a table of error correction codes of the present invention made by adding module-2 to AAH in the code string set of FIG. 2 (c).

Claims (5)

최장부호열발생기에 위해 7비트의 최장부호열을 발생하는 단계와, 상기 7비트의 최장부호열을 1비트씩 시프트하여 7개의 부호열을 만들고 그 7개의 부호열 처음에 "0"비트를 각각 추가하여 코드길이가 8인 7개의 부호열을만드는 단계와, 상기 코드길이가 8인 7개의 부호열에 "0000 0000"의 코드워드를 추가하려 8개의 코드워드를 만들고, 그 8개 코드워드 각각의 정반대(Antipodal)값을 코드워드로 만들어 총 16개의 코드워드를 만드는 단계와,상기 16개의 코드워드에 "AAH"값을 각기 모듈-2 가산시켜 에러정정코드를 만들고 그 에러정정코드에 의해 에러정정코드 엔코딩테이블을 만드는 단계와, 상기 에러정정코드 엔코딩테이블을 역으로 하여 추출된 값에 의해에러정정코드 디코딩테이블을 만드는 단계로 이루어지는 것을 특징으로 하는 에러정정코드 작성방법.Generating a 7-bit longest code string for the longest code string generator, shifting the 7-bit longest code string by 1 bit to form 7 code strings, and each of the "0" bits at the beginning of the 7 code strings, respectively. Adding seven code strings having a code length of eight, and adding eight codewords of " 0000 0000 " to the seven code strings having a code length of eight; 16 codewords are made by making antipodal values into codewords, and module-2 is added to each of the 16 codewords by "AAH" to generate an error correction code and error correction by the error correction code. And generating an error correction code decoding table based on a value extracted by reversing the error correction code encoding table. 제 1 항에 있어서, 7비트의 최장부호열은 "111 0100"인 것을 특징으로 하는 에러정정코드 작성방법.The method of claim 1, wherein the longest code string of 7 bits is " 111 0100. " 제 1 항에 있어서, 에러정정코드 엔코딩테이블은 8비트의 전송정보를 4비트씩으로 분할하여 그의 어드레스를 지정하는 것임을 특징으로 하는 에러정정코드 작성방법.The method of claim 1, wherein the error correction code encoding table divides 8-bit transmission information into 4 bits and designates an address thereof. 제 1 항에 있어서, 에러정정코드 디코딩테이블은 8비트 수신정보에 의해 그의 어드레스를 지정하는 것임을 특징으로 하는 에러정정코드 작성방법.2. The method of claim 1, wherein the error correction code decoding table specifies its address by 8-bit received information. 제 4 항에 있어서, 에러정정코드 디코딩테이블은 8비트 수신정보에서 1비트의 에러가 발생될 수 있는 8가지 경우의 어드레스를 갖고, 그 8가지 경우의 어드레스 내용은 원래 전송정보가 동일하게 기록되어 있는 것임을 특징으로 하는 에러정정코드 작성방법.The error correcting code decoding table according to claim 4, wherein the error correction code decoding table has eight cases of addresses in which 1-bit error can be generated in the 8-bit received information. Error correction code writing method characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930024143A 1993-11-13 1993-11-13 Error correction code method KR950010769B1 (en)

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KR950010769B1 KR950010769B1 (en) 1995-09-22

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324742B1 (en) * 1999-01-14 2002-02-20 구자홍 Code assignment method for encoder

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003242902A1 (en) * 2002-06-20 2004-01-06 Koninklijke Philips Electronics N.V. Balanced disparity channel code for dc control

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100324742B1 (en) * 1999-01-14 2002-02-20 구자홍 Code assignment method for encoder

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