KR950013034A

KR950013034A - Transmission Clock Reception Switching Circuit

Info

Publication number: KR950013034A
Application number: KR1019930022221A
Authority: KR
Inventors: 최성철
Original assignee: 정장호; 금성정보통신 주식회사
Priority date: 1993-10-25
Filing date: 1993-10-25
Publication date: 1995-05-17
Also published as: KR950011622B1

Abstract

본 발명은 교환시스템의 망동기장치에 구비된 PLL(Phase Locked Loop)회로에 비교기준클럭으로서 공급되는 전송클럭을 절체하는 전송클럭 수신절체회로에 관한 것으로, 특히 전송클럭 절체를 자동으로 수행함으로써 망동기 장치의 PLL 회로의 동작정지를 방지하여 안정된 망동기를 유지시키도록 한 전송클럭수신 절체회로에 관한 것이다.The present invention relates to a transmission clock reception switching circuit for switching a transmission clock supplied as a reference reference clock to a PLL (Phase Locked Loop) circuit provided in a network synchronizer of an exchange system, and in particular, a network by automatically performing a transfer clock switching. The present invention relates to a transmission clock reception switching circuit which prevents operation of the PLL circuit of a synchronous device to maintain a stable network synchronizer.

종래의 전송클럭수신절체회로는 수신버퍼(11)를 통해 공급되는 클럭이 E1클럭에서 T1클럭으로 바뀌거나 T1클럭에서 E1클럭으로 바뀌는 경우 선택단자(P1-P5)의 연결을 수동으로 변경해야하므로, 신속하게 전송클럭을 절체할 수 없으며 선택단자(P1~P5)의 연결을 변경하는 동안에 망동기장치의 PLL회로에 대한 비교기준클럭공급이 중단되어 망동기가 불안정하게 되는 문제점이 있었다.In the conventional transmission clock reception circuit, when the clock supplied through the reception buffer 11 is changed from E1 clock to T1 clock or from T1 clock to E1 clock, the connection of the selection terminals P1-P5 must be changed manually. In other words, the transmission clock cannot be switched quickly, and the reference clock supply to the PLL circuit of the network synchronizer device is interrupted while the connection of the selection terminals P1 to P5 is changed.

본 발명은 수신되는 전송클럭절체시 자동으로 신속하게 절체할 수 있으며, 전송클럭절체시 망동기장치에 구비된 PLL회로에 공급되는 비교기준클럭의 중단을 방지하여 망동기를 안정되게 유지할 수 있는 효과가 있다.The present invention can be switched quickly and automatically when the transmission clock is received, and the effect of maintaining a stable starter by preventing the interruption of the reference reference clock supplied to the PLL circuit provided in the network starter device at the time of the transfer clock transfer have.

Description

Transmission Clock Reception Switching Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 전송클럭 수신절체회로 구성도.2 is a block diagram of a transmission clock reception switching circuit according to the present invention.

Claims

In the transmission clock reception switching circuit, an input selection circuit 30 for receiving E1 and T1 clocks by selecting one of two input terminals 11 and 12, and band-filtering the T1 clock supplied from the input selection circuit 30; A state of the first band pass filter 31, the second band pass filter 32 which filters the E1 clock supplied from the input selection circuit 30, and the T1 clock supplied from the first band pass filter 31 A first search circuit 33 for detecting a first state signal and outputting a first state signal, and a second search circuit 34 for detecting a state of the E1 clock supplied from the second band pass filter 32 and outputting a second state signal. ), A state control circuit 37 and a state control circuit 37 for outputting a clock selection control signal and a division control signal according to the first and second state signals and controlling the selection of an input terminal of the input selection circuit 30. The first and second band pass filters 31, according to the clock selection control signal supplied from A clock selection circuit 35 which selects and outputs one of the clocks from the clock 32, and divides the clock from the clock selection circuit 35 at a predetermined number of times in accordance with the division control signal supplied from the state control circuit 37; And a phase comparison clock raw component period (36) which is supplied as a reference reference clock to the PLL circuit side of the network synchronizer device.

※ Note: The disclosure is based on the initial application.