KR950012243A - Processor State Management Method in Distributed System Using Processor State Information Table - Google Patents

Processor State Management Method in Distributed System Using Processor State Information Table Download PDF

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Publication number
KR950012243A
KR950012243A KR1019930021723A KR930021723A KR950012243A KR 950012243 A KR950012243 A KR 950012243A KR 1019930021723 A KR1019930021723 A KR 1019930021723A KR 930021723 A KR930021723 A KR 930021723A KR 950012243 A KR950012243 A KR 950012243A
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South Korea
Prior art keywords
processor
state
test
information table
omp
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KR1019930021723A
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Korean (ko)
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KR960014178B1 (en
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김현숙
김철수
김한경
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양승택
재단법인 한국전자통신연구소
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

Abstract

본 발명은 전전자교환기와 같은 분산처리 시스템에서 운용 및 유지 보수 프로세서(Operation and Maintenance Perocessor; 이하, OMP라 함)에 부하를 주지 않고 프로세서 상태정보테이블을 이용한 프로세서 상태관리 방법에 관한 것으로, 상기 OMP(1)가 상태 시험을 하고자 하는 프로세서로 상태시험을 요구하고 관련 타이머를 작동하게 하면 상태시허믈 요구받은 프로세서가 자신의 상태를 시험하는 제1 단계(15,16); 사기 제1 단계(15,16)수행후, 시험 결과가 정상이면 상태시험완료메시지를 OMP(1)로 보내고 타이머 완료하게 하며 다음에 위치한 프로세서를 시험하도록 요구하는 제2 단계(17,18); 상기 제1 단계(15,16)수행 후, 프로세서 상태가 비정상이면 비정상 상태임을 상태정보 테이블에 기록하여 다음에 위치한 프로세서로 상태시험 요구메시지를 송신하고 관련 타이머를 작동하게 하는 제3단계(19,20); 및 상기 제2단계(17,18) 및 제3단계(19,20) 수행 후 마지막 프로세서의 상태를 시험할 때까지 반복하고 마지막 프로세서를 시험한 후 상태 정보테이블을 OPM(1)로 보내고 종료하는 제4단계(21,22)를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a processor state management method using a processor state information table without load on an operation and maintenance processor (OMP) in a distributed processing system such as an electronic switch. A first step (15, 16) in which (1) requests a state test to a processor to be subjected to a state test and causes the associated timer to operate, and the state-requested processor tests its state; A second step (17, 18) of performing a fraudulent first step (15, 16), if the test result is normal, sending a status test completion message to the OMP (1), causing the timer to complete, and testing the next located processor; After performing the first step (15, 16), if the processor state is abnormal, the third step (19, to record the abnormal state in the status information table to send a status test request message to the next processor and to operate the associated timer) 20); And repeating until the state of the last processor is tested after performing the second steps (17, 18) and the third step (19, 20), and after the test of the last processor, sends the state information table to the OPM (1) and terminates. It is characterized by comprising a fourth step (21, 22).

Description

프로세서 상태정보테이블을 이용한 분산시스팀에서의 프로세서 상태관리 방법Processor State Management Method in Distributed System Using Processor State Information Table

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명이 적용된 ATM교환기의 각 모듈별 프로세서 구성도.1 is a processor configuration diagram of each module of the ATM switch to which the present invention is applied.

제2도는 본 발명에 따른 프로세서 상태 관리 방법에 대한 처리 흐름도.2 is a process flow diagram for a processor state management method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : OMP(Operation and Maintenance Processor)1: OMP (Operation and Maintenance Processor)

2 : NSCP(Network Synchroization Control Processor)2: Network Synchroization Control Processor (NSCP)

3 : MMCP(Man Machine Control Processor)3: MMCP (Man Machine Control Processor)

4,11 : BCP(Broadcasting Call Processor)4,11: BCP (Broadcasting Call Processor)

5 : CIMP(Central Interconnection Maintenance Processor)5: CIMP (Central Interconnection Maintenance Processor)

6 : RCIP(Remote Center Interface Processor)6: RCIP (Remote Center Interface Processor)

7 : GSP(Global Service Proocessor)7: GSP (Global Service Proocessor)

8,13 : NTP(Number Traslation Processor)8,13: NTP (Number Traslation Processor)

9 : SCP(Subscriber Call Processor)9: SCP (Subscriber Call Processor)

10 : TCP(Trunk Call Processor)10: TCP Call Processor

12 : ASMP(Access Switching Maintenance Processor)12: ASMP (Access Switching Maintenance Processor)

14 : SH(Signalling Handler)14: SH (Signalling Handler)

Claims (1)

OMP(Operation and Maintenance Processor)(1), NSCP(Network Synchronization Control Processor)(2), MMCP(Man Machine Control Processor)(3), BCP(Broadcasting Call Processor)(4),(11)CIMP(Central Interconnection Maintenance Processor)(5), RCIP(Remote Center Interface Processor)(6), GSP(Global Service Processor)(7), NTP(Number Translation processor)(8),(13) SCP(Subscriber Call Processor)(9), TCP(Trunk Call Processor)(10), ASMP(Access Switiching Maintenance Processr)(12), SH(Signalling Handler)(14)를 구비하는 교환기에 적용되는 프로세서 상태관리 방법에 있어서, 상기 OMP(1)가 상태 시험을 하고자 하는 프로세서로 상태시험을 요구하고 관련 타이머를 작동하게 하면 상태시험을 요구받은 프로세서가 자신의 상태를 시험하는 제1단계(15, 16); 상기 제1단계(15, 16) 수행 후, 시험결과가 정상이면 상태시험완료메시지를 상기 OMP(1)로 보내고 타이머를 완료하게 하며 다음에 위치한 프로세서를 시험하도록 요구하는 제2단계(17, 18); 상기 제1단계(15, 16) 수행후, 프로세서 상태가 비정상이면 비정상 상태임을 상태정보테이블에 기록하여 다음에 위치한 프로세서로 상태시험요구메시지를 송신하고 관련 타이머를 작동하게 하는 제3단계(19, 20); 및 상기 제2단계(17, 18) 및 제3단계(19, 20) 수행후, 마지막 프로세서의 상태를 시험할 때까지 반복하고 마지막 프로세서를 시험한 후 상태 정보테이블을 상기 OMP(1)로 보내고 종료하는 제4단계(21, 22)를 포함하여 이루어지는 것을 특징으로 하는 프로세서 상태정보테이블을 이용한 분산시스팀에서의 프로세서 상태관리 방법.Operation and Maintenance Processor (OMP) (1), Network Synchronization Control Processor (NSCP) (2), Man Machine Control Processor (MMCP) (3), Broadcasting Call Processor (BCP) (4), (11) Central Interconnection Maintenance Processor (5), Remote Center Interface Processor (RCIP) (6), Global Service Processor (GSP) (7), Number Translation processor (NTP) (8), (13) Subscriber Call Processor (9) A processor state management method applied to an exchange having a TCP (Trunk Call Processor) 10, an Access Switiching Maintenance Processor (ASMP) 12, and a Signaling Handler (SH) 14, wherein the OMP 1 A first step (15, 16) of requesting a state test to a processor to be state-tested and operating an associated timer, the processor having received the state-tested state test its own state; After the first steps (15, 16), if the test results are normal, the second step (17, 18) to send a status test completion message to the OMP (1) to complete the timer and to test the next processor located ); After performing the first steps (15, 16), if the processor state is abnormal, the third step (19, to record the abnormal state in the status information table to send a status test request message to the next processor to operate the associated timer) 20); And after performing the second steps (17, 18) and the third step (19, 20), repeats until the state of the last processor is tested, and after testing the last processor, sends a status information table to the OMP (1). And a fourth step (21, 22) of terminating the processor state management method in the distributed system using the processor state information table. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930021723A 1993-10-19 1993-10-19 Atm electronic switching exchanger KR960014178B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930021723A KR960014178B1 (en) 1993-10-19 1993-10-19 Atm electronic switching exchanger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021723A KR960014178B1 (en) 1993-10-19 1993-10-19 Atm electronic switching exchanger

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KR950012243A true KR950012243A (en) 1995-05-16
KR960014178B1 KR960014178B1 (en) 1996-10-14

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