KR950010490Y1 - Checking circuit of delay frequency - Google Patents

Abstract

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Description

Delay frequency test circuit

1 is a delay frequency test circuit of the present invention.

2a to c is a waveform diagram of the input frequency (S1) (S2) (S3) of the present invention.

3a to h is an output waveform diagram of each part of the present invention.

* Explanation of symbols for main parts of the drawings

10,20,30: Comparator 40,50,60: Flip Flop

70,80: beta red ogate 90: reference pulse generator

100,110: counter 120,130: indicator

The present invention relates to a delay frequency check circuit, and more particularly, to a delay frequency check circuit that makes it possible to easily determine the delay degree numerically and to simultaneously identify a large number of frequency delays.

In the past, an oscilloscope was used to determine the degree of delay of an output waveform with respect to an arbitrary input waveform.

However, when the waveform is input to the oscilloscope, it is inconvenient to visually check the delay and the number of frequency delays is limited. There was a problem.

In order to solve this problem, the present invention displays a delay degree of an arbitrary delay frequency with respect to a reference frequency as a counter so that the delay degree can be discriminated ten times and a large number of delay frequencies can be simultaneously identified. To provide.

1 is a delay frequency check circuit diagram of the present invention. As shown in FIG. 1, comparators 10, 20, and 30 outputting waveforms by comparing input frequencies S1, S2, S3, and reference voltage Verf, respectively. ), The flip waveform 40 which receives the output waveform of the comparator 10 as the clock signal CK1 and outputs the reference pulse Q1, and the output signal Q1 of the flip flip 40 are data signals. Flip flips 50 and 60 which are respectively input to D2 and D3 and receive the output signals of the comparators 20 and 30 and output delay pulses Q2 and Q3, respectively. Exclusive ogates 70 and 80 which receive the output pulse Q1 of 40 and the output pulses 50 and 60 of flip flip 50 and 60, respectively, and perform exclusive logic, 1 MHz The output signal of the exclusive or gate 70 and 80 is counted in synchronization with the output signal of the reference pulse generator 90 and the reference pulse generator 90 to generate a reference pulse of the display 120. Show at 130 Is to be configured as a counter 110 and 120, the flip peulreup (40,50,60) has a data input (D1 of the initial signal (V _O) is connected to the clear terminal (CLR) and the flip peulreup 40 ) Is configured to apply a DC voltage (5V).

When described in detail with reference to the accompanying drawings, the operation, effects of the present invention configured as described above.

First, the initial signals V _O are applied to the clear terminals CLR of the flip-flops 30, 40, and 50 to initialize the flip-flops 30, 40, and 50, and then the reference voltage Vref. When the input frequencies S1, S2, and S3 shown in FIG. 2 are respectively input to the other input terminals of the comparators 10, 20 and 30 commonly applied to the one input terminal, the comparators 10 and 20 are respectively input. 30 compares the two signals and outputs an output waveform having a duty rate of 1: 5T and a period of 6T as shown in FIGS. 3a, b, and c, respectively, by clocks of the flip planes 30, 40, and 50; Output to the terminals CK1 (CK2) (CK3). Here, the reference voltage Vref is about 0.86V.

In this case, since the input frequency S2 is a frequency delayed by 120 ° with respect to the input frequency S1, and the input frequency S3 is a frequency delayed by 240 ° with respect to the input frequency S1, the comparator 20 The output waveform (FIG. 3B) is generated after being delayed for 2T period than the output waveform (FIG. 3A) of the comparator 10, and the output waveform (FIG. 3C) of the comparator 30 is It occurs after a delay of 4T period than the output waveform (Fig. 3a).

Accordingly, the output waveform of the flip flop 40 becomes high (H) at the rising edge of the waveform output from the comparator 10 as shown in FIG. 3d, and the waveform is the exclusive ogate 70 (80). Is applied to one side input terminal and the data input D2 of the flip flop 50, respectively.

The flip flop 50 outputs a waveform such as a third e-degree that becomes high (H) at the rising edge of the comparison paper 20 delayed for 2T period than the flip flop 40, thereby providing Applied to the other input terminal, and the flip flip 60 outputs a waveform equal to a third degree of high (H) at the rising edge of the comparator 30 delayed for 4T period than the flip flip 40 by the exclusive operation. It is applied to the other input terminal of the ora gate 80.

Accordingly, the exclusive ogates 70 and 80 output waveforms such as 3f and h, respectively.

At this time, the counter 100 reads the high (H) signal of the 2T period output from the exclusive ogate 70 in synchronization with the reference pulse of 1 MHz output from the reference pulse generator 90, and then reads it to the display 120. The counter 110 reads the high (H) signal of the 4T period output from the exclusive or gate 80 in synchronization with the 1 MHz reference pulse output from the reference pulse generator 90 and displays the display 130. ).

Accordingly, the degree of delay of the delay frequency with respect to the reference frequency can be known through the indicators 120 and 130.

In this case, the 1 MHz reference pulse output from the reference pulse generator 90 should be higher than the output waveforms of the exclusive ogates 70 and 80 input to the counters 100 and 110. .

As described above, the present invention can easily determine the delay of a frequency delayed by a predetermined period from the reference frequency with a counter, and in particular, it is possible to simultaneously determine a large number of frequency delays.

Claims (4)

Comparator 10, 20, 30 for outputting a waveform by comparing the input frequencies S1, S2, S3 and the reference voltage Vref, respectively, and inputting the output waveforms of the comparator 10 as clock signals. The flip pulse 40 receives the reference pulse and the output signal of the flip flip 40 as a data signal, and receives the output signals of the comparators 20 and 30, respectively, and outputs a delay pulse. 50 and 60, and an exclusive oragate 70 and 80 which receive an output pulse of the flip flip 40 and an output pulse of the flip flip 50 and 60 respectively and perform an exclusive OR. A reference pulse generator 90 for generating a reference pulse of MHz and an output signal of the exclusive ogates 70 and 80 in synchronization with the output signal of the reference pulse generator 90; In synchronization with the output signal of the reference pulse generator 90, the output signals of the exclusive oragate 70 and 80 are counted and displayed on the display 120 and 130. Delay frequency test circuit, characterized in that configured in the counter 110 (120). The delay frequency checking circuit according to claim 1, wherein the input frequency (S2) is delayed by 120 degrees from the input frequency (S1). 2. The delay frequency checking circuit according to claim 1, wherein the input frequency (S3) is delayed by 240 [deg.] Than the input frequency (S1). 2. The delay frequency checking circuit according to claim 1, wherein the reference pulse for synchronizing the counter (100) (110) is a frequency higher than an input waveform of the counter (100) (110).